272 lines
7.2 KiB
C
272 lines
7.2 KiB
C
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/delay.h>
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#include "mt76x2.h"
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#include "mt76x2_mcu.h"
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#include "mt76x2_eeprom.h"
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#include "mt76x2_trace.h"
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void mt76x2_mac_set_bssid(struct mt76x2_dev *dev, u8 idx, const u8 *addr)
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{
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idx &= 7;
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mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
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mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
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get_unaligned_le16(addr + 4));
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}
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void mt76x2_mac_poll_tx_status(struct mt76x2_dev *dev, bool irq)
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{
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struct mt76x2_tx_status stat = {};
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unsigned long flags;
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u8 update = 1;
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bool ret;
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if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
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return;
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trace_mac_txstat_poll(dev);
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while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) {
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spin_lock_irqsave(&dev->irq_lock, flags);
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ret = mt76x2_mac_load_tx_status(dev, &stat);
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spin_unlock_irqrestore(&dev->irq_lock, flags);
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if (!ret)
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break;
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trace_mac_txstat_fetch(dev, &stat);
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if (!irq) {
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mt76x2_send_tx_status(dev, &stat, &update);
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continue;
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}
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kfifo_put(&dev->txstatus_fifo, stat);
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}
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}
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static void
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mt76x2_mac_queue_txdone(struct mt76x2_dev *dev, struct sk_buff *skb,
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void *txwi_ptr)
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{
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struct mt76x2_tx_info *txi = mt76x2_skb_tx_info(skb);
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struct mt76x2_txwi *txwi = txwi_ptr;
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mt76x2_mac_poll_tx_status(dev, false);
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txi->tries = 0;
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txi->jiffies = jiffies;
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txi->wcid = txwi->wcid;
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txi->pktid = txwi->pktid;
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trace_mac_txdone_add(dev, txwi->wcid, txwi->pktid);
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mt76x2_tx_complete(dev, skb);
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}
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void mt76x2_mac_process_tx_status_fifo(struct mt76x2_dev *dev)
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{
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struct mt76x2_tx_status stat;
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u8 update = 1;
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while (kfifo_get(&dev->txstatus_fifo, &stat))
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mt76x2_send_tx_status(dev, &stat, &update);
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}
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void mt76x2_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q,
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struct mt76_queue_entry *e, bool flush)
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{
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struct mt76x2_dev *dev = container_of(mdev, struct mt76x2_dev, mt76);
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if (e->txwi)
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mt76x2_mac_queue_txdone(dev, e->skb, &e->txwi->txwi);
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else
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dev_kfree_skb_any(e->skb);
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}
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static int
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mt76_write_beacon(struct mt76x2_dev *dev, int offset, struct sk_buff *skb)
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{
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int beacon_len = dev->beacon_offsets[1] - dev->beacon_offsets[0];
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struct mt76x2_txwi txwi;
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if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x2_txwi)))
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return -ENOSPC;
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mt76x2_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len);
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mt76_wr_copy(dev, offset, &txwi, sizeof(txwi));
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offset += sizeof(txwi);
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mt76_wr_copy(dev, offset, skb->data, skb->len);
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return 0;
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}
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static int
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__mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 bcn_idx, struct sk_buff *skb)
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{
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int beacon_len = dev->beacon_offsets[1] - dev->beacon_offsets[0];
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int beacon_addr = dev->beacon_offsets[bcn_idx];
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int ret = 0;
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int i;
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/* Prevent corrupt transmissions during update */
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mt76_set(dev, MT_BCN_BYPASS_MASK, BIT(bcn_idx));
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if (skb) {
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ret = mt76_write_beacon(dev, beacon_addr, skb);
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if (!ret)
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dev->beacon_data_mask |= BIT(bcn_idx);
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} else {
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dev->beacon_data_mask &= ~BIT(bcn_idx);
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for (i = 0; i < beacon_len; i += 4)
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mt76_wr(dev, beacon_addr + i, 0);
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}
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mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xff00 | ~dev->beacon_data_mask);
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return ret;
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}
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int mt76x2_mac_set_beacon(struct mt76x2_dev *dev, u8 vif_idx,
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struct sk_buff *skb)
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{
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bool force_update = false;
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int bcn_idx = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(dev->beacons); i++) {
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if (vif_idx == i) {
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force_update = !!dev->beacons[i] ^ !!skb;
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if (dev->beacons[i])
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dev_kfree_skb(dev->beacons[i]);
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dev->beacons[i] = skb;
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__mt76x2_mac_set_beacon(dev, bcn_idx, skb);
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} else if (force_update && dev->beacons[i]) {
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__mt76x2_mac_set_beacon(dev, bcn_idx, dev->beacons[i]);
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}
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bcn_idx += !!dev->beacons[i];
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}
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for (i = bcn_idx; i < ARRAY_SIZE(dev->beacons); i++) {
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if (!(dev->beacon_data_mask & BIT(i)))
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break;
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__mt76x2_mac_set_beacon(dev, i, NULL);
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}
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mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N,
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bcn_idx - 1);
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return 0;
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}
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void mt76x2_mac_set_beacon_enable(struct mt76x2_dev *dev, u8 vif_idx, bool val)
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{
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u8 old_mask = dev->beacon_mask;
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bool en;
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u32 reg;
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if (val) {
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dev->beacon_mask |= BIT(vif_idx);
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} else {
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dev->beacon_mask &= ~BIT(vif_idx);
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mt76x2_mac_set_beacon(dev, vif_idx, NULL);
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}
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if (!!old_mask == !!dev->beacon_mask)
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return;
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en = dev->beacon_mask;
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mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
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reg = MT_BEACON_TIME_CFG_BEACON_TX |
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MT_BEACON_TIME_CFG_TBTT_EN |
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MT_BEACON_TIME_CFG_TIMER_EN;
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mt76_rmw(dev, MT_BEACON_TIME_CFG, reg, reg * en);
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if (en)
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mt76x2_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
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else
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mt76x2_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
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}
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void mt76x2_update_channel(struct mt76_dev *mdev)
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{
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struct mt76x2_dev *dev = container_of(mdev, struct mt76x2_dev, mt76);
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struct mt76_channel_state *state;
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u32 active, busy;
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state = mt76_channel_state(&dev->mt76, dev->mt76.chandef.chan);
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busy = mt76_rr(dev, MT_CH_BUSY);
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active = busy + mt76_rr(dev, MT_CH_IDLE);
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spin_lock_bh(&dev->mt76.cc_lock);
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state->cc_busy += busy;
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state->cc_active += active;
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spin_unlock_bh(&dev->mt76.cc_lock);
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}
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void mt76x2_mac_work(struct work_struct *work)
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{
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struct mt76x2_dev *dev = container_of(work, struct mt76x2_dev,
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mac_work.work);
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int i, idx;
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mt76x2_update_channel(&dev->mt76);
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for (i = 0, idx = 0; i < 16; i++) {
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u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
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dev->aggr_stats[idx++] += val & 0xffff;
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dev->aggr_stats[idx++] += val >> 16;
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}
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ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mac_work,
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MT_CALIBRATE_INTERVAL);
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}
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void mt76x2_mac_set_tx_protection(struct mt76x2_dev *dev, u32 val)
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{
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u32 data = 0;
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if (val != ~0)
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data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) |
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MT_PROT_CFG_RTS_THRESH;
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mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val);
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mt76_rmw(dev, MT_CCK_PROT_CFG,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_OFDM_PROT_CFG,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_MM20_PROT_CFG,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_MM40_PROT_CFG,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_GF20_PROT_CFG,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_GF40_PROT_CFG,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_TX_PROT_CFG6,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_TX_PROT_CFG7,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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mt76_rmw(dev, MT_TX_PROT_CFG8,
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MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
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}
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