500 lines
13 KiB
C
500 lines
13 KiB
C
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/delay.h>
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#include "mt76x2.h"
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#include "mt76x2_mcu.h"
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#include "mt76x2_eeprom.h"
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static bool
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mt76x2_phy_tssi_init_cal(struct mt76x2_dev *dev)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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u32 flag = 0;
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if (!mt76x2_tssi_enabled(dev))
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return false;
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if (mt76x2_channel_silent(dev))
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return false;
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if (chan->band == NL80211_BAND_5GHZ)
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flag |= BIT(0);
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if (mt76x2_ext_pa_enabled(dev, chan->band))
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flag |= BIT(8);
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mt76x2_mcu_calibrate(dev, MCU_CAL_TSSI, flag);
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dev->cal.tssi_cal_done = true;
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return true;
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}
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static void
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mt76x2_phy_channel_calibrate(struct mt76x2_dev *dev, bool mac_stopped)
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{
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struct ieee80211_channel *chan = dev->mt76.chandef.chan;
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bool is_5ghz = chan->band == NL80211_BAND_5GHZ;
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if (dev->cal.channel_cal_done)
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return;
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if (mt76x2_channel_silent(dev))
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return;
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if (!dev->cal.tssi_cal_done)
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mt76x2_phy_tssi_init_cal(dev);
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if (!mac_stopped)
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mt76x2_mac_stop(dev, false);
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if (is_5ghz)
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mt76x2_mcu_calibrate(dev, MCU_CAL_LC, 0);
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mt76x2_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz);
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mt76x2_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz);
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mt76x2_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz);
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mt76x2_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0);
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mt76x2_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0);
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if (!mac_stopped)
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mt76x2_mac_resume(dev);
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mt76x2_apply_gain_adj(dev);
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dev->cal.channel_cal_done = true;
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}
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void mt76x2_phy_set_antenna(struct mt76x2_dev *dev)
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{
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u32 val;
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val = mt76_rr(dev, MT_BBP(AGC, 0));
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val &= ~(BIT(4) | BIT(1));
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switch (dev->mt76.antenna_mask) {
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case 1:
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/* disable mac DAC control */
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mt76_clear(dev, MT_BBP(IBI, 9), BIT(11));
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mt76_clear(dev, MT_BBP(TXBE, 5), 3);
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mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0x3);
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mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2);
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/* disable DAC 1 */
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mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4);
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val &= ~(BIT(3) | BIT(0));
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break;
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case 2:
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/* disable mac DAC control */
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mt76_clear(dev, MT_BBP(IBI, 9), BIT(11));
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mt76_rmw_field(dev, MT_BBP(TXBE, 5), 3, 1);
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mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0xc);
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mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1);
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/* disable DAC 0 */
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mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1);
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val &= ~BIT(3);
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val |= BIT(0);
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break;
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case 3:
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default:
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/* enable mac DAC control */
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mt76_set(dev, MT_BBP(IBI, 9), BIT(11));
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mt76_set(dev, MT_BBP(TXBE, 5), 3);
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mt76_rmw_field(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT, 0xf);
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mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20));
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mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9));
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val &= ~BIT(0);
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val |= BIT(3);
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break;
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}
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mt76_wr(dev, MT_BBP(AGC, 0), val);
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}
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static void
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mt76x2_get_agc_gain(struct mt76x2_dev *dev, u8 *dest)
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{
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dest[0] = mt76_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
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dest[1] = mt76_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
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}
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static int
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mt76x2_get_rssi_gain_thresh(struct mt76x2_dev *dev)
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{
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switch (dev->mt76.chandef.width) {
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case NL80211_CHAN_WIDTH_80:
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return -62;
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case NL80211_CHAN_WIDTH_40:
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return -65;
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default:
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return -68;
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}
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}
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static int
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mt76x2_get_low_rssi_gain_thresh(struct mt76x2_dev *dev)
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{
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switch (dev->mt76.chandef.width) {
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case NL80211_CHAN_WIDTH_80:
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return -76;
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case NL80211_CHAN_WIDTH_40:
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return -79;
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default:
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return -82;
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}
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}
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static void
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mt76x2_phy_set_gain_val(struct mt76x2_dev *dev)
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{
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u32 val;
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u8 gain_val[2];
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gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
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gain_val[1] = dev->cal.agc_gain_cur[1] - dev->cal.agc_gain_adjust;
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if (dev->mt76.chandef.width >= NL80211_CHAN_WIDTH_40)
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val = 0x1e42 << 16;
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else
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val = 0x1836 << 16;
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val |= 0xf8;
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mt76_wr(dev, MT_BBP(AGC, 8),
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val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[0]));
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mt76_wr(dev, MT_BBP(AGC, 9),
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val | FIELD_PREP(MT_BBP_AGC_GAIN, gain_val[1]));
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if (dev->mt76.chandef.chan->flags & IEEE80211_CHAN_RADAR)
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mt76x2_dfs_adjust_agc(dev);
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}
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static void
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mt76x2_phy_adjust_vga_gain(struct mt76x2_dev *dev)
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{
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u32 false_cca;
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u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
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false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, mt76_rr(dev, MT_RX_STAT_1));
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dev->cal.false_cca = false_cca;
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if (false_cca > 800 && dev->cal.agc_gain_adjust < limit)
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dev->cal.agc_gain_adjust += 2;
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else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
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(dev->cal.agc_gain_adjust >= limit && false_cca < 500))
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dev->cal.agc_gain_adjust -= 2;
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else
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return;
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mt76x2_phy_set_gain_val(dev);
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}
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static void
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mt76x2_phy_update_channel_gain(struct mt76x2_dev *dev)
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{
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u8 *gain = dev->cal.agc_gain_init;
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u8 low_gain_delta, gain_delta;
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bool gain_change;
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int low_gain;
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u32 val;
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dev->cal.avg_rssi_all = mt76x2_phy_get_min_avg_rssi(dev);
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low_gain = (dev->cal.avg_rssi_all > mt76x2_get_rssi_gain_thresh(dev)) +
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(dev->cal.avg_rssi_all > mt76x2_get_low_rssi_gain_thresh(dev));
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gain_change = (dev->cal.low_gain & 2) ^ (low_gain & 2);
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dev->cal.low_gain = low_gain;
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if (!gain_change) {
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mt76x2_phy_adjust_vga_gain(dev);
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return;
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}
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if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80) {
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mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211);
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val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf;
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if (low_gain == 2)
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val |= 0x3;
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else
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val |= 0x5;
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mt76_wr(dev, MT_BBP(AGC, 26), val);
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} else {
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mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423);
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}
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if (mt76x2_has_ext_lna(dev))
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low_gain_delta = 10;
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else
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low_gain_delta = 14;
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if (low_gain == 2) {
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mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990);
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mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808);
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mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808);
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gain_delta = low_gain_delta;
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dev->cal.agc_gain_adjust = 0;
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} else {
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mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991);
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if (dev->mt76.chandef.width == NL80211_CHAN_WIDTH_80)
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mt76_wr(dev, MT_BBP(AGC, 35), 0x10101014);
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else
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mt76_wr(dev, MT_BBP(AGC, 35), 0x11111116);
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mt76_wr(dev, MT_BBP(AGC, 37), 0x2121262C);
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gain_delta = 0;
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dev->cal.agc_gain_adjust = low_gain_delta;
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}
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dev->cal.agc_gain_cur[0] = gain[0] - gain_delta;
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dev->cal.agc_gain_cur[1] = gain[1] - gain_delta;
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mt76x2_phy_set_gain_val(dev);
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/* clear false CCA counters */
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mt76_rr(dev, MT_RX_STAT_1);
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}
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int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
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struct cfg80211_chan_def *chandef)
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{
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struct ieee80211_channel *chan = chandef->chan;
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bool scan = test_bit(MT76_SCANNING, &dev->mt76.state);
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enum nl80211_band band = chan->band;
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u8 channel;
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u32 ext_cca_chan[4] = {
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[0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
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[1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
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[2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
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[3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
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FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
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};
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int ch_group_index;
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u8 bw, bw_index;
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int freq, freq1;
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int ret;
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dev->cal.channel_cal_done = false;
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freq = chandef->chan->center_freq;
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freq1 = chandef->center_freq1;
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channel = chan->hw_value;
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switch (chandef->width) {
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case NL80211_CHAN_WIDTH_40:
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bw = 1;
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if (freq1 > freq) {
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bw_index = 1;
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ch_group_index = 0;
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} else {
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bw_index = 3;
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ch_group_index = 1;
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}
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channel += 2 - ch_group_index * 4;
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break;
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case NL80211_CHAN_WIDTH_80:
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ch_group_index = (freq - freq1 + 30) / 20;
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if (WARN_ON(ch_group_index < 0 || ch_group_index > 3))
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ch_group_index = 0;
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bw = 2;
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bw_index = ch_group_index;
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channel += 6 - ch_group_index * 4;
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break;
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default:
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bw = 0;
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bw_index = 0;
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ch_group_index = 0;
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break;
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}
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mt76x2_read_rx_gain(dev);
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mt76x2_phy_set_txpower_regs(dev, band);
|
||
|
|
mt76x2_configure_tx_delay(dev, band, bw);
|
||
|
|
mt76x2_phy_set_txpower(dev);
|
||
|
|
|
||
|
|
mt76x2_phy_set_band(dev, chan->band, ch_group_index & 1);
|
||
|
|
mt76x2_phy_set_bw(dev, chandef->width, ch_group_index);
|
||
|
|
|
||
|
|
mt76_rmw(dev, MT_EXT_CCA_CFG,
|
||
|
|
(MT_EXT_CCA_CFG_CCA0 |
|
||
|
|
MT_EXT_CCA_CFG_CCA1 |
|
||
|
|
MT_EXT_CCA_CFG_CCA2 |
|
||
|
|
MT_EXT_CCA_CFG_CCA3 |
|
||
|
|
MT_EXT_CCA_CFG_CCA_MASK),
|
||
|
|
ext_cca_chan[ch_group_index]);
|
||
|
|
|
||
|
|
ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
mt76x2_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true);
|
||
|
|
|
||
|
|
mt76x2_phy_set_antenna(dev);
|
||
|
|
|
||
|
|
/* Enable LDPC Rx */
|
||
|
|
if (mt76xx_rev(dev) >= MT76XX_REV_E3)
|
||
|
|
mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
|
||
|
|
|
||
|
|
if (!dev->cal.init_cal_done) {
|
||
|
|
u8 val = mt76x2_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
|
||
|
|
|
||
|
|
if (val != 0xff)
|
||
|
|
mt76x2_mcu_calibrate(dev, MCU_CAL_R, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
mt76x2_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel);
|
||
|
|
|
||
|
|
/* Rx LPF calibration */
|
||
|
|
if (!dev->cal.init_cal_done)
|
||
|
|
mt76x2_mcu_calibrate(dev, MCU_CAL_RC, 0);
|
||
|
|
|
||
|
|
dev->cal.init_cal_done = true;
|
||
|
|
|
||
|
|
mt76_wr(dev, MT_BBP(AGC, 61), 0xFF64A4E2);
|
||
|
|
mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010);
|
||
|
|
mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404);
|
||
|
|
mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
|
||
|
|
mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x04101B3F);
|
||
|
|
|
||
|
|
if (scan)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
dev->cal.low_gain = -1;
|
||
|
|
mt76x2_phy_channel_calibrate(dev, true);
|
||
|
|
mt76x2_get_agc_gain(dev, dev->cal.agc_gain_init);
|
||
|
|
memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
|
||
|
|
sizeof(dev->cal.agc_gain_cur));
|
||
|
|
|
||
|
|
/* init default values for temp compensation */
|
||
|
|
if (mt76x2_tssi_enabled(dev)) {
|
||
|
|
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
|
||
|
|
0x38);
|
||
|
|
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
|
||
|
|
0x38);
|
||
|
|
}
|
||
|
|
|
||
|
|
ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work,
|
||
|
|
MT_CALIBRATE_INTERVAL);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
mt76x2_phy_tssi_compensate(struct mt76x2_dev *dev)
|
||
|
|
{
|
||
|
|
struct ieee80211_channel *chan = dev->mt76.chandef.chan;
|
||
|
|
struct mt76x2_tx_power_info txp;
|
||
|
|
struct mt76x2_tssi_comp t = {};
|
||
|
|
|
||
|
|
if (!dev->cal.tssi_cal_done)
|
||
|
|
return;
|
||
|
|
|
||
|
|
if (!dev->cal.tssi_comp_pending) {
|
||
|
|
/* TSSI trigger */
|
||
|
|
t.cal_mode = BIT(0);
|
||
|
|
mt76x2_mcu_tssi_comp(dev, &t);
|
||
|
|
dev->cal.tssi_comp_pending = true;
|
||
|
|
} else {
|
||
|
|
if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
|
||
|
|
return;
|
||
|
|
|
||
|
|
dev->cal.tssi_comp_pending = false;
|
||
|
|
mt76x2_get_power_info(dev, &txp, chan);
|
||
|
|
|
||
|
|
if (mt76x2_ext_pa_enabled(dev, chan->band))
|
||
|
|
t.pa_mode = 1;
|
||
|
|
|
||
|
|
t.cal_mode = BIT(1);
|
||
|
|
t.slope0 = txp.chain[0].tssi_slope;
|
||
|
|
t.offset0 = txp.chain[0].tssi_offset;
|
||
|
|
t.slope1 = txp.chain[1].tssi_slope;
|
||
|
|
t.offset1 = txp.chain[1].tssi_offset;
|
||
|
|
mt76x2_mcu_tssi_comp(dev, &t);
|
||
|
|
|
||
|
|
if (t.pa_mode || dev->cal.dpd_cal_done)
|
||
|
|
return;
|
||
|
|
|
||
|
|
usleep_range(10000, 20000);
|
||
|
|
mt76x2_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value);
|
||
|
|
dev->cal.dpd_cal_done = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
mt76x2_phy_temp_compensate(struct mt76x2_dev *dev)
|
||
|
|
{
|
||
|
|
struct mt76x2_temp_comp t;
|
||
|
|
int temp, db_diff;
|
||
|
|
|
||
|
|
if (mt76x2_get_temp_comp(dev, &t))
|
||
|
|
return;
|
||
|
|
|
||
|
|
temp = mt76_get_field(dev, MT_TEMP_SENSOR, MT_TEMP_SENSOR_VAL);
|
||
|
|
temp -= t.temp_25_ref;
|
||
|
|
temp = (temp * 1789) / 1000 + 25;
|
||
|
|
dev->cal.temp = temp;
|
||
|
|
|
||
|
|
if (temp > 25)
|
||
|
|
db_diff = (temp - 25) / t.high_slope;
|
||
|
|
else
|
||
|
|
db_diff = (25 - temp) / t.low_slope;
|
||
|
|
|
||
|
|
db_diff = min(db_diff, t.upper_bound);
|
||
|
|
db_diff = max(db_diff, t.lower_bound);
|
||
|
|
|
||
|
|
mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
|
||
|
|
db_diff * 2);
|
||
|
|
mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
|
||
|
|
db_diff * 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
void mt76x2_phy_calibrate(struct work_struct *work)
|
||
|
|
{
|
||
|
|
struct mt76x2_dev *dev;
|
||
|
|
|
||
|
|
dev = container_of(work, struct mt76x2_dev, cal_work.work);
|
||
|
|
mt76x2_phy_channel_calibrate(dev, false);
|
||
|
|
mt76x2_phy_tssi_compensate(dev);
|
||
|
|
mt76x2_phy_temp_compensate(dev);
|
||
|
|
mt76x2_phy_update_channel_gain(dev);
|
||
|
|
ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work,
|
||
|
|
MT_CALIBRATE_INTERVAL);
|
||
|
|
}
|
||
|
|
|
||
|
|
int mt76x2_phy_start(struct mt76x2_dev *dev)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = mt76x2_mcu_set_radio_state(dev, true);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|