582 lines
13 KiB
C
582 lines
13 KiB
C
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/* $Id: avmcard.h,v 1.1.4.1.2.1 2001/12/21 15:00:17 kai Exp $
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*
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* Copyright 1999 by Carsten Paeth <calle@calle.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#ifndef _AVMCARD_H_
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#define _AVMCARD_H_
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#define AVMB1_PORTLEN 0x1f
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#define AVM_MAXVERSION 8
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#define AVM_NCCI_PER_CHANNEL 4
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/*
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* Versions
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*/
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#define VER_DRIVER 0
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#define VER_CARDTYPE 1
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#define VER_HWID 2
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#define VER_SERIAL 3
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#define VER_OPTION 4
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#define VER_PROTO 5
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#define VER_PROFILE 6
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#define VER_CAPI 7
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enum avmcardtype {
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avm_b1isa,
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avm_b1pci,
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avm_b1pcmcia,
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avm_m1,
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avm_m2,
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avm_t1isa,
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avm_t1pci,
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avm_c4,
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avm_c2
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};
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typedef struct avmcard_dmabuf {
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long size;
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u8 *dmabuf;
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dma_addr_t dmaaddr;
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} avmcard_dmabuf;
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typedef struct avmcard_dmainfo {
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u32 recvlen;
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avmcard_dmabuf recvbuf;
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avmcard_dmabuf sendbuf;
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struct sk_buff_head send_queue;
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struct pci_dev *pcidev;
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} avmcard_dmainfo;
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typedef struct avmctrl_info {
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char cardname[32];
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int versionlen;
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char versionbuf[1024];
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char *version[AVM_MAXVERSION];
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char infobuf[128]; /* for function procinfo */
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struct avmcard *card;
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struct capi_ctr capi_ctrl;
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struct list_head ncci_head;
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} avmctrl_info;
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typedef struct avmcard {
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char name[32];
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spinlock_t lock;
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unsigned int port;
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unsigned irq;
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unsigned long membase;
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enum avmcardtype cardtype;
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unsigned char revision;
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unsigned char class;
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int cardnr; /* for t1isa */
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char msgbuf[128]; /* capimsg msg part */
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char databuf[2048]; /* capimsg data part */
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void __iomem *mbase;
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volatile u32 csr;
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avmcard_dmainfo *dma;
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struct avmctrl_info *ctrlinfo;
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u_int nr_controllers;
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u_int nlogcontr;
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struct list_head list;
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} avmcard;
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extern int b1_irq_table[16];
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/*
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* LLI Messages to the ISDN-ControllerISDN Controller
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*/
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#define SEND_POLL 0x72 /*
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* after load <- RECEIVE_POLL
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*/
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#define SEND_INIT 0x11 /*
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* first message <- RECEIVE_INIT
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* int32 NumApplications int32
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* NumNCCIs int32 BoardNumber
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*/
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#define SEND_REGISTER 0x12 /*
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* register an application int32
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* ApplIDId int32 NumMessages
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* int32 NumB3Connections int32
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* NumB3Blocks int32 B3Size
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*
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* AnzB3Connection != 0 &&
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* AnzB3Blocks >= 1 && B3Size >= 1
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*/
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#define SEND_RELEASE 0x14 /*
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* deregister an application int32
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* ApplID
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*/
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#define SEND_MESSAGE 0x15 /*
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* send capi-message int32 length
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* capi-data ...
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*/
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#define SEND_DATA_B3_REQ 0x13 /*
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* send capi-data-message int32
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* MsgLength capi-data ... int32
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* B3Length data ....
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*/
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#define SEND_CONFIG 0x21 /*
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*/
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#define SEND_POLLACK 0x73 /* T1 Watchdog */
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/*
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* LLI Messages from the ISDN-ControllerISDN Controller
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*/
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#define RECEIVE_POLL 0x32 /*
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* <- after SEND_POLL
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*/
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#define RECEIVE_INIT 0x27 /*
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* <- after SEND_INIT int32 length
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* byte total length b1struct board
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* driver revision b1struct card
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* type b1struct reserved b1struct
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* serial number b1struct driver
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* capability b1struct d-channel
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* protocol b1struct CAPI-2.0
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* profile b1struct capi version
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*/
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#define RECEIVE_MESSAGE 0x21 /*
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* <- after SEND_MESSAGE int32
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* AppllID int32 Length capi-data
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* ....
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*/
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#define RECEIVE_DATA_B3_IND 0x22 /*
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* received data int32 AppllID
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* int32 Length capi-data ...
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* int32 B3Length data ...
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*/
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#define RECEIVE_START 0x23 /*
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* Handshake
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*/
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#define RECEIVE_STOP 0x24 /*
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* Handshake
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*/
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#define RECEIVE_NEW_NCCI 0x25 /*
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* int32 AppllID int32 NCCI int32
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* WindowSize
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*/
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#define RECEIVE_FREE_NCCI 0x26 /*
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* int32 AppllID int32 NCCI
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*/
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#define RECEIVE_RELEASE 0x26 /*
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* int32 AppllID int32 0xffffffff
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*/
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#define RECEIVE_TASK_READY 0x31 /*
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* int32 tasknr
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* int32 Length Taskname ...
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*/
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#define RECEIVE_DEBUGMSG 0x71 /*
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* int32 Length message
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*
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*/
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#define RECEIVE_POLLDWORD 0x75 /* t1pci in dword mode */
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#define WRITE_REGISTER 0x00
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#define READ_REGISTER 0x01
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/*
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* port offsets
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*/
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#define B1_READ 0x00
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#define B1_WRITE 0x01
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#define B1_INSTAT 0x02
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#define B1_OUTSTAT 0x03
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#define B1_ANALYSE 0x04
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#define B1_REVISION 0x05
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#define B1_RESET 0x10
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#define B1_STAT0(cardtype) ((cardtype) == avm_m1 ? 0x81200000l : 0x80A00000l)
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#define B1_STAT1(cardtype) (0x80E00000l)
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/* ---------------------------------------------------------------- */
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static inline unsigned char b1outp(unsigned int base,
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unsigned short offset,
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unsigned char value)
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{
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outb(value, base + offset);
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return inb(base + B1_ANALYSE);
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}
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static inline int b1_rx_full(unsigned int base)
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{
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return inb(base + B1_INSTAT) & 0x1;
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}
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static inline unsigned char b1_get_byte(unsigned int base)
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{
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unsigned long stop = jiffies + 1 * HZ; /* maximum wait time 1 sec */
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while (!b1_rx_full(base) && time_before(jiffies, stop));
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if (b1_rx_full(base))
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return inb(base + B1_READ);
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printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base);
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return 0;
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}
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static inline unsigned int b1_get_word(unsigned int base)
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{
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unsigned int val = 0;
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val |= b1_get_byte(base);
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val |= (b1_get_byte(base) << 8);
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val |= (b1_get_byte(base) << 16);
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val |= (b1_get_byte(base) << 24);
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return val;
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}
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static inline int b1_tx_empty(unsigned int base)
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{
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return inb(base + B1_OUTSTAT) & 0x1;
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}
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static inline void b1_put_byte(unsigned int base, unsigned char val)
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{
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while (!b1_tx_empty(base));
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b1outp(base, B1_WRITE, val);
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}
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static inline int b1_save_put_byte(unsigned int base, unsigned char val)
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{
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unsigned long stop = jiffies + 2 * HZ;
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while (!b1_tx_empty(base) && time_before(jiffies, stop));
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if (!b1_tx_empty(base)) return -1;
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b1outp(base, B1_WRITE, val);
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return 0;
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}
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static inline void b1_put_word(unsigned int base, unsigned int val)
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{
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b1_put_byte(base, val & 0xff);
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b1_put_byte(base, (val >> 8) & 0xff);
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b1_put_byte(base, (val >> 16) & 0xff);
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b1_put_byte(base, (val >> 24) & 0xff);
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}
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static inline unsigned int b1_get_slice(unsigned int base,
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unsigned char *dp)
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{
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unsigned int len, i;
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len = i = b1_get_word(base);
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while (i-- > 0) *dp++ = b1_get_byte(base);
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return len;
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}
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static inline void b1_put_slice(unsigned int base,
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unsigned char *dp, unsigned int len)
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{
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unsigned i = len;
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b1_put_word(base, i);
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while (i-- > 0)
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b1_put_byte(base, *dp++);
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}
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static void b1_wr_reg(unsigned int base,
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unsigned int reg,
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unsigned int value)
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{
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b1_put_byte(base, WRITE_REGISTER);
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b1_put_word(base, reg);
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b1_put_word(base, value);
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}
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static inline unsigned int b1_rd_reg(unsigned int base,
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unsigned int reg)
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{
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b1_put_byte(base, READ_REGISTER);
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b1_put_word(base, reg);
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return b1_get_word(base);
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}
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static inline void b1_reset(unsigned int base)
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{
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b1outp(base, B1_RESET, 0);
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mdelay(55 * 2); /* 2 TIC's */
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b1outp(base, B1_RESET, 1);
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mdelay(55 * 2); /* 2 TIC's */
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b1outp(base, B1_RESET, 0);
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mdelay(55 * 2); /* 2 TIC's */
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}
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static inline unsigned char b1_disable_irq(unsigned int base)
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{
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return b1outp(base, B1_INSTAT, 0x00);
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}
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/* ---------------------------------------------------------------- */
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static inline void b1_set_test_bit(unsigned int base,
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enum avmcardtype cardtype,
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int onoff)
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{
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b1_wr_reg(base, B1_STAT0(cardtype), onoff ? 0x21 : 0x20);
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}
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static inline int b1_get_test_bit(unsigned int base,
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enum avmcardtype cardtype)
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{
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return (b1_rd_reg(base, B1_STAT0(cardtype)) & 0x01) != 0;
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}
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/* ---------------------------------------------------------------- */
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#define T1_FASTLINK 0x00
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#define T1_SLOWLINK 0x08
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#define T1_READ B1_READ
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#define T1_WRITE B1_WRITE
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#define T1_INSTAT B1_INSTAT
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#define T1_OUTSTAT B1_OUTSTAT
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#define T1_IRQENABLE 0x05
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#define T1_FIFOSTAT 0x06
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#define T1_RESETLINK 0x10
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#define T1_ANALYSE 0x11
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#define T1_IRQMASTER 0x12
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#define T1_IDENT 0x17
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#define T1_RESETBOARD 0x1f
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#define T1F_IREADY 0x01
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#define T1F_IHALF 0x02
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#define T1F_IFULL 0x04
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#define T1F_IEMPTY 0x08
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#define T1F_IFLAGS 0xF0
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#define T1F_OREADY 0x10
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#define T1F_OHALF 0x20
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#define T1F_OEMPTY 0x40
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#define T1F_OFULL 0x80
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#define T1F_OFLAGS 0xF0
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/* there are HEMA cards with 1k and 4k FIFO out */
|
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|
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#define FIFO_OUTBSIZE 256
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#define FIFO_INPBSIZE 512
|
||
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#define HEMA_VERSION_ID 0
|
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|
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#define HEMA_PAL_ID 0
|
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|
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static inline void t1outp(unsigned int base,
|
||
|
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unsigned short offset,
|
||
|
|
unsigned char value)
|
||
|
|
{
|
||
|
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outb(value, base + offset);
|
||
|
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}
|
||
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|
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static inline unsigned char t1inp(unsigned int base,
|
||
|
|
unsigned short offset)
|
||
|
|
{
|
||
|
|
return inb(base + offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int t1_isfastlink(unsigned int base)
|
||
|
|
{
|
||
|
|
return (inb(base + T1_IDENT) & ~0x82) == 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned char t1_fifostatus(unsigned int base)
|
||
|
|
{
|
||
|
|
return inb(base + T1_FIFOSTAT);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline unsigned int t1_get_slice(unsigned int base,
|
||
|
|
unsigned char *dp)
|
||
|
|
{
|
||
|
|
unsigned int len, i;
|
||
|
|
#ifdef FASTLINK_DEBUG
|
||
|
|
unsigned wcnt = 0, bcnt = 0;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
len = i = b1_get_word(base);
|
||
|
|
if (t1_isfastlink(base)) {
|
||
|
|
int status;
|
||
|
|
while (i > 0) {
|
||
|
|
status = t1_fifostatus(base) & (T1F_IREADY | T1F_IHALF);
|
||
|
|
if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
|
||
|
|
|
||
|
|
switch (status) {
|
||
|
|
case T1F_IREADY | T1F_IHALF | T1F_IFULL:
|
||
|
|
insb(base + B1_READ, dp, FIFO_INPBSIZE);
|
||
|
|
dp += FIFO_INPBSIZE;
|
||
|
|
i -= FIFO_INPBSIZE;
|
||
|
|
#ifdef FASTLINK_DEBUG
|
||
|
|
wcnt += FIFO_INPBSIZE;
|
||
|
|
#endif
|
||
|
|
break;
|
||
|
|
case T1F_IREADY | T1F_IHALF:
|
||
|
|
insb(base + B1_READ, dp, i);
|
||
|
|
#ifdef FASTLINK_DEBUG
|
||
|
|
wcnt += i;
|
||
|
|
#endif
|
||
|
|
dp += i;
|
||
|
|
i = 0;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
*dp++ = b1_get_byte(base);
|
||
|
|
i--;
|
||
|
|
#ifdef FASTLINK_DEBUG
|
||
|
|
bcnt++;
|
||
|
|
#endif
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#ifdef FASTLINK_DEBUG
|
||
|
|
if (wcnt)
|
||
|
|
printk(KERN_DEBUG "b1lli(0x%x): get_slice l=%d w=%d b=%d\n",
|
||
|
|
base, len, wcnt, bcnt);
|
||
|
|
#endif
|
||
|
|
} else {
|
||
|
|
while (i-- > 0)
|
||
|
|
*dp++ = b1_get_byte(base);
|
||
|
|
}
|
||
|
|
return len;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void t1_put_slice(unsigned int base,
|
||
|
|
unsigned char *dp, unsigned int len)
|
||
|
|
{
|
||
|
|
unsigned i = len;
|
||
|
|
b1_put_word(base, i);
|
||
|
|
if (t1_isfastlink(base)) {
|
||
|
|
int status;
|
||
|
|
while (i > 0) {
|
||
|
|
status = t1_fifostatus(base) & (T1F_OREADY | T1F_OHALF);
|
||
|
|
if (i >= FIFO_OUTBSIZE) status |= T1F_OEMPTY;
|
||
|
|
switch (status) {
|
||
|
|
case T1F_OREADY | T1F_OHALF | T1F_OEMPTY:
|
||
|
|
outsb(base + B1_WRITE, dp, FIFO_OUTBSIZE);
|
||
|
|
dp += FIFO_OUTBSIZE;
|
||
|
|
i -= FIFO_OUTBSIZE;
|
||
|
|
break;
|
||
|
|
case T1F_OREADY | T1F_OHALF:
|
||
|
|
outsb(base + B1_WRITE, dp, i);
|
||
|
|
dp += i;
|
||
|
|
i = 0;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
b1_put_byte(base, *dp++);
|
||
|
|
i--;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
while (i-- > 0)
|
||
|
|
b1_put_byte(base, *dp++);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void t1_disable_irq(unsigned int base)
|
||
|
|
{
|
||
|
|
t1outp(base, T1_IRQMASTER, 0x00);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void t1_reset(unsigned int base)
|
||
|
|
{
|
||
|
|
/* reset T1 Controller */
|
||
|
|
b1_reset(base);
|
||
|
|
/* disable irq on HEMA */
|
||
|
|
t1outp(base, B1_INSTAT, 0x00);
|
||
|
|
t1outp(base, B1_OUTSTAT, 0x00);
|
||
|
|
t1outp(base, T1_IRQMASTER, 0x00);
|
||
|
|
/* reset HEMA board configuration */
|
||
|
|
t1outp(base, T1_RESETBOARD, 0xf);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void b1_setinterrupt(unsigned int base, unsigned irq,
|
||
|
|
enum avmcardtype cardtype)
|
||
|
|
{
|
||
|
|
switch (cardtype) {
|
||
|
|
case avm_t1isa:
|
||
|
|
t1outp(base, B1_INSTAT, 0x00);
|
||
|
|
t1outp(base, B1_INSTAT, 0x02);
|
||
|
|
t1outp(base, T1_IRQMASTER, 0x08);
|
||
|
|
break;
|
||
|
|
case avm_b1isa:
|
||
|
|
b1outp(base, B1_INSTAT, 0x00);
|
||
|
|
b1outp(base, B1_RESET, b1_irq_table[irq]);
|
||
|
|
b1outp(base, B1_INSTAT, 0x02);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
case avm_m1:
|
||
|
|
case avm_m2:
|
||
|
|
case avm_b1pci:
|
||
|
|
b1outp(base, B1_INSTAT, 0x00);
|
||
|
|
b1outp(base, B1_RESET, 0xf0);
|
||
|
|
b1outp(base, B1_INSTAT, 0x02);
|
||
|
|
break;
|
||
|
|
case avm_c4:
|
||
|
|
case avm_t1pci:
|
||
|
|
b1outp(base, B1_RESET, 0xf0);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* b1.c */
|
||
|
|
avmcard *b1_alloc_card(int nr_controllers);
|
||
|
|
void b1_free_card(avmcard *card);
|
||
|
|
int b1_detect(unsigned int base, enum avmcardtype cardtype);
|
||
|
|
void b1_getrevision(avmcard *card);
|
||
|
|
int b1_load_t4file(avmcard *card, capiloaddatapart *t4file);
|
||
|
|
int b1_load_config(avmcard *card, capiloaddatapart *config);
|
||
|
|
int b1_loaded(avmcard *card);
|
||
|
|
|
||
|
|
int b1_load_firmware(struct capi_ctr *ctrl, capiloaddata *data);
|
||
|
|
void b1_reset_ctr(struct capi_ctr *ctrl);
|
||
|
|
void b1_register_appl(struct capi_ctr *ctrl, u16 appl,
|
||
|
|
capi_register_params *rp);
|
||
|
|
void b1_release_appl(struct capi_ctr *ctrl, u16 appl);
|
||
|
|
u16 b1_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
|
||
|
|
void b1_parse_version(avmctrl_info *card);
|
||
|
|
irqreturn_t b1_interrupt(int interrupt, void *devptr);
|
||
|
|
|
||
|
|
int b1_proc_show(struct seq_file *m, void *v);
|
||
|
|
|
||
|
|
avmcard_dmainfo *avmcard_dma_alloc(char *name, struct pci_dev *,
|
||
|
|
long rsize, long ssize);
|
||
|
|
void avmcard_dma_free(avmcard_dmainfo *);
|
||
|
|
|
||
|
|
/* b1dma.c */
|
||
|
|
int b1pciv4_detect(avmcard *card);
|
||
|
|
int t1pci_detect(avmcard *card);
|
||
|
|
void b1dma_reset(avmcard *card);
|
||
|
|
irqreturn_t b1dma_interrupt(int interrupt, void *devptr);
|
||
|
|
|
||
|
|
int b1dma_load_firmware(struct capi_ctr *ctrl, capiloaddata *data);
|
||
|
|
void b1dma_reset_ctr(struct capi_ctr *ctrl);
|
||
|
|
void b1dma_remove_ctr(struct capi_ctr *ctrl);
|
||
|
|
void b1dma_register_appl(struct capi_ctr *ctrl,
|
||
|
|
u16 appl,
|
||
|
|
capi_register_params *rp);
|
||
|
|
void b1dma_release_appl(struct capi_ctr *ctrl, u16 appl);
|
||
|
|
u16 b1dma_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
|
||
|
|
int b1dma_proc_show(struct seq_file *m, void *v);
|
||
|
|
|
||
|
|
#endif /* _AVMCARD_H_ */
|