312 lines
8.3 KiB
C
312 lines
8.3 KiB
C
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/*
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* Copyright (C) 2013 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PERCPU_H
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#define __ASM_PERCPU_H
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#include <linux/preempt.h>
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#include <asm/alternative.h>
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#include <asm/cmpxchg.h>
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#include <asm/stack_pointer.h>
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static inline void set_my_cpu_offset(unsigned long off)
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{
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asm volatile(ALTERNATIVE("msr tpidr_el1, %0",
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"msr tpidr_el2, %0",
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ARM64_HAS_VIRT_HOST_EXTN)
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:: "r" (off) : "memory");
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}
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static inline unsigned long __my_cpu_offset(void)
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{
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unsigned long off;
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/*
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* We want to allow caching the value, so avoid using volatile and
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* instead use a fake stack read to hazard against barrier().
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*/
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asm(ALTERNATIVE("mrs %0, tpidr_el1",
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"mrs %0, tpidr_el2",
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ARM64_HAS_VIRT_HOST_EXTN)
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: "=r" (off) :
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"Q" (*(const unsigned long *)current_stack_pointer));
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return off;
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}
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#define __my_cpu_offset __my_cpu_offset()
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#define PERCPU_OP(op, asm_op) \
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static inline unsigned long __percpu_##op(void *ptr, \
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unsigned long val, int size) \
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{ \
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unsigned long loop, ret; \
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\
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switch (size) { \
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case 1: \
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asm ("//__per_cpu_" #op "_1\n" \
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"1: ldxrb %w[ret], %[ptr]\n" \
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#asm_op " %w[ret], %w[ret], %w[val]\n" \
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" stxrb %w[loop], %w[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u8 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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case 2: \
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asm ("//__per_cpu_" #op "_2\n" \
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"1: ldxrh %w[ret], %[ptr]\n" \
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#asm_op " %w[ret], %w[ret], %w[val]\n" \
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" stxrh %w[loop], %w[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u16 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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case 4: \
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asm ("//__per_cpu_" #op "_4\n" \
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"1: ldxr %w[ret], %[ptr]\n" \
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#asm_op " %w[ret], %w[ret], %w[val]\n" \
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" stxr %w[loop], %w[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u32 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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case 8: \
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asm ("//__per_cpu_" #op "_8\n" \
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"1: ldxr %[ret], %[ptr]\n" \
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#asm_op " %[ret], %[ret], %[val]\n" \
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" stxr %w[loop], %[ret], %[ptr]\n" \
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" cbnz %w[loop], 1b" \
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: [loop] "=&r" (loop), [ret] "=&r" (ret), \
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[ptr] "+Q"(*(u64 *)ptr) \
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: [val] "Ir" (val)); \
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break; \
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default: \
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ret = 0; \
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BUILD_BUG(); \
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} \
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\
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return ret; \
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}
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PERCPU_OP(add, add)
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PERCPU_OP(and, and)
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PERCPU_OP(or, orr)
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#undef PERCPU_OP
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static inline unsigned long __percpu_read(void *ptr, int size)
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{
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unsigned long ret;
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switch (size) {
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case 1:
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ret = READ_ONCE(*(u8 *)ptr);
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break;
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case 2:
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ret = READ_ONCE(*(u16 *)ptr);
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break;
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case 4:
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ret = READ_ONCE(*(u32 *)ptr);
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break;
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case 8:
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ret = READ_ONCE(*(u64 *)ptr);
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break;
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default:
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ret = 0;
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BUILD_BUG();
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}
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return ret;
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}
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static inline void __percpu_write(void *ptr, unsigned long val, int size)
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{
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switch (size) {
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case 1:
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WRITE_ONCE(*(u8 *)ptr, (u8)val);
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break;
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case 2:
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WRITE_ONCE(*(u16 *)ptr, (u16)val);
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break;
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case 4:
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WRITE_ONCE(*(u32 *)ptr, (u32)val);
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break;
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case 8:
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WRITE_ONCE(*(u64 *)ptr, (u64)val);
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break;
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default:
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BUILD_BUG();
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}
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}
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static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
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int size)
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{
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unsigned long ret, loop;
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switch (size) {
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case 1:
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asm ("//__percpu_xchg_1\n"
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"1: ldxrb %w[ret], %[ptr]\n"
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" stxrb %w[loop], %w[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u8 *)ptr)
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: [val] "r" (val));
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break;
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case 2:
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asm ("//__percpu_xchg_2\n"
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"1: ldxrh %w[ret], %[ptr]\n"
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" stxrh %w[loop], %w[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u16 *)ptr)
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: [val] "r" (val));
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break;
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case 4:
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asm ("//__percpu_xchg_4\n"
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"1: ldxr %w[ret], %[ptr]\n"
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" stxr %w[loop], %w[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u32 *)ptr)
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: [val] "r" (val));
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break;
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case 8:
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asm ("//__percpu_xchg_8\n"
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"1: ldxr %[ret], %[ptr]\n"
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" stxr %w[loop], %[val], %[ptr]\n"
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" cbnz %w[loop], 1b"
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: [loop] "=&r"(loop), [ret] "=&r"(ret),
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[ptr] "+Q"(*(u64 *)ptr)
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: [val] "r" (val));
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break;
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default:
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ret = 0;
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BUILD_BUG();
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}
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return ret;
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}
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/* this_cpu_cmpxchg */
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#define _protect_cmpxchg_local(pcp, o, n) \
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({ \
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typeof(*raw_cpu_ptr(&(pcp))) __ret; \
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preempt_disable(); \
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__ret = cmpxchg_local(raw_cpu_ptr(&(pcp)), o, n); \
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preempt_enable(); \
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__ret; \
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})
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#define this_cpu_cmpxchg_1(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_2(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_4(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_8(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \
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({ \
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int __ret; \
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preempt_disable(); \
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__ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \
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raw_cpu_ptr(&(ptr2)), \
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o1, o2, n1, n2); \
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preempt_enable(); \
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__ret; \
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})
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#define _percpu_read(pcp) \
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({ \
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typeof(pcp) __retval; \
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preempt_disable_notrace(); \
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__retval = (typeof(pcp))__percpu_read(raw_cpu_ptr(&(pcp)), \
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sizeof(pcp)); \
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preempt_enable_notrace(); \
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__retval; \
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})
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#define _percpu_write(pcp, val) \
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do { \
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preempt_disable_notrace(); \
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__percpu_write(raw_cpu_ptr(&(pcp)), (unsigned long)(val), \
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sizeof(pcp)); \
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preempt_enable_notrace(); \
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} while(0) \
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#define _pcp_protect(operation, pcp, val) \
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({ \
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typeof(pcp) __retval; \
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preempt_disable(); \
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__retval = (typeof(pcp))operation(raw_cpu_ptr(&(pcp)), \
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(val), sizeof(pcp)); \
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preempt_enable(); \
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__retval; \
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})
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#define _percpu_add(pcp, val) \
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_pcp_protect(__percpu_add, pcp, val)
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#define _percpu_add_return(pcp, val) _percpu_add(pcp, val)
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#define _percpu_and(pcp, val) \
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_pcp_protect(__percpu_and, pcp, val)
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#define _percpu_or(pcp, val) \
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_pcp_protect(__percpu_or, pcp, val)
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#define _percpu_xchg(pcp, val) (typeof(pcp)) \
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_pcp_protect(__percpu_xchg, pcp, (unsigned long)(val))
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#define this_cpu_add_1(pcp, val) _percpu_add(pcp, val)
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#define this_cpu_add_2(pcp, val) _percpu_add(pcp, val)
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#define this_cpu_add_4(pcp, val) _percpu_add(pcp, val)
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#define this_cpu_add_8(pcp, val) _percpu_add(pcp, val)
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#define this_cpu_add_return_1(pcp, val) _percpu_add_return(pcp, val)
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#define this_cpu_add_return_2(pcp, val) _percpu_add_return(pcp, val)
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#define this_cpu_add_return_4(pcp, val) _percpu_add_return(pcp, val)
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#define this_cpu_add_return_8(pcp, val) _percpu_add_return(pcp, val)
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#define this_cpu_and_1(pcp, val) _percpu_and(pcp, val)
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#define this_cpu_and_2(pcp, val) _percpu_and(pcp, val)
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#define this_cpu_and_4(pcp, val) _percpu_and(pcp, val)
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#define this_cpu_and_8(pcp, val) _percpu_and(pcp, val)
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#define this_cpu_or_1(pcp, val) _percpu_or(pcp, val)
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#define this_cpu_or_2(pcp, val) _percpu_or(pcp, val)
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#define this_cpu_or_4(pcp, val) _percpu_or(pcp, val)
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#define this_cpu_or_8(pcp, val) _percpu_or(pcp, val)
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#define this_cpu_read_1(pcp) _percpu_read(pcp)
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#define this_cpu_read_2(pcp) _percpu_read(pcp)
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#define this_cpu_read_4(pcp) _percpu_read(pcp)
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#define this_cpu_read_8(pcp) _percpu_read(pcp)
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#define this_cpu_write_1(pcp, val) _percpu_write(pcp, val)
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#define this_cpu_write_2(pcp, val) _percpu_write(pcp, val)
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#define this_cpu_write_4(pcp, val) _percpu_write(pcp, val)
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#define this_cpu_write_8(pcp, val) _percpu_write(pcp, val)
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#define this_cpu_xchg_1(pcp, val) _percpu_xchg(pcp, val)
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#define this_cpu_xchg_2(pcp, val) _percpu_xchg(pcp, val)
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#define this_cpu_xchg_4(pcp, val) _percpu_xchg(pcp, val)
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#define this_cpu_xchg_8(pcp, val) _percpu_xchg(pcp, val)
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#include <asm-generic/percpu.h>
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#endif /* __ASM_PERCPU_H */
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