203 lines
3.8 KiB
ArmAsm
203 lines
3.8 KiB
ArmAsm
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/*
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* linux/arch/unicore32/kernel/sleep.S
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Maintained by GUAN Xue-tao <gxt@mprc.pku.edu.cn>
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* Copyright (C) 2001-2010 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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.text
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pkunity_cpu_save_cp:
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@ get coprocessor registers
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movc r3, p0.c7, #0 @ PID
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movc r4, p0.c2, #0 @ translation table base addr
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movc r5, p0.c1, #0 @ control reg
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@ store them plus current virtual stack ptr on stack
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mov r6, sp
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stm.w (r3 - r6), [sp-]
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mov pc, lr
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pkunity_cpu_save_sp:
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@ preserve phys address of stack
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mov r0, sp
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stw.w lr, [sp+], #-4
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b.l sleep_phys_sp
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ldw r1, =sleep_save_sp
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stw r0, [r1]
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ldw.w pc, [sp]+, #4
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/*
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* puv3_cpu_suspend()
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*
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* Forces CPU into sleep state.
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*
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* r0 = value for PWRMODE M field for desired sleep state
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*/
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ENTRY(puv3_cpu_suspend)
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stm.w (r16 - r27, lr), [sp-] @ save registers on stack
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stm.w (r4 - r15), [sp-] @ save registers on stack
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#ifdef CONFIG_UNICORE_FPU_F64
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sfm.w (f0 - f7 ), [sp-]
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sfm.w (f8 - f15), [sp-]
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sfm.w (f16 - f23), [sp-]
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sfm.w (f24 - f31), [sp-]
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cff r4, s31
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stm.w (r4), [sp-]
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#endif
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b.l pkunity_cpu_save_cp
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b.l pkunity_cpu_save_sp
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@ clean data cache
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mov r1, #0
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movc p0.c5, r1, #14
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nop
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nop
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nop
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nop
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@ DDR2 BaseAddr
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ldw r0, =(PKUNITY_DDR2CTRL_BASE)
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@ PM BaseAddr
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ldw r1, =(PKUNITY_PM_BASE)
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@ set PLL_SYS_CFG reg, 275
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movl r6, #0x00002401
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stw r6, [r1+], #0x18
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@ set PLL_DDR_CFG reg, 66MHz
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movl r6, #0x00100c00
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stw r6, [r1+], #0x1c
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@ set wake up source
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movl r8, #0x800001ff @ epip4d
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stw r8, [r1+], #0xc
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@ set PGSR
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movl r5, #0x40000
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stw r5, [r1+], #0x10
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@ prepare DDR2 refresh settings
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ldw r5, [r0+], #0x24
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or r5, r5, #0x00000001
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@ prepare PMCR for PLL changing
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movl r6, #0xc
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@ prepare for closing PLL
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movl r7, #0x1
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@ prepare sleep mode
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mov r8, #0x1
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@ movl r0, 0x11111111
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@ put_word_ocd r0
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b pkunity_cpu_do_suspend
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.ltorg
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.align 5
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pkunity_cpu_do_suspend:
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b 101f
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@ put DDR2 into self-refresh
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100: stw r5, [r0+], #0x24
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@ change PLL
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stw r6, [r1]
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b 1f
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.ltorg
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.align 5
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101: b 102f
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@ wait for PLL changing complete
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1: ldw r6, [r1+], #0x44
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csub.a r6, #0x1
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bne 1b
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b 2f
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.ltorg
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.align 5
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102: b 100b
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@ close PLL
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2: stw r7, [r1+], #0x4
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@ enter sleep mode
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stw r8, [r1]
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3: b 3b
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/*
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* puv3_cpu_resume()
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*
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* entry point from bootloader into kernel during resume
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*
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* Note: Yes, part of the following code is located into the .data section.
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* This is to allow sleep_save_sp to be accessed with a relative load
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* while we can't rely on any MMU translation. We could have put
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* sleep_save_sp in the .text section as well, but some setups might
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* insist on it to be truly read-only.
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*/
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.data
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.align 5
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ENTRY(puv3_cpu_resume)
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@ movl r0, 0x20202020
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@ put_word_ocd r0
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ldw r0, sleep_save_sp @ stack phys addr
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ldw r2, =resume_after_mmu @ its absolute virtual address
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ldm (r3 - r6), [r0]+ @ CP regs + virt stack ptr
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mov sp, r6 @ CP regs + virt stack ptr
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mov r1, #0
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movc p0.c6, r1, #6 @ invalidate I & D TLBs
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movc p0.c5, r1, #28 @ invalidate I & D caches, BTB
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movc p0.c7, r3, #0 @ PID
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movc p0.c2, r4, #0 @ translation table base addr
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movc p0.c1, r5, #0 @ control reg, turn on mmu
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nop
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jump r2
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nop
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nop
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nop
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nop
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nop
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sleep_save_sp:
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.word 0 @ preserve stack phys ptr here
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.text
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resume_after_mmu:
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@ movl r0, 0x30303030
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@ put_word_ocd r0
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#ifdef CONFIG_UNICORE_FPU_F64
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lfm.w (f0 - f7 ), [sp]+
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lfm.w (f8 - f15), [sp]+
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lfm.w (f16 - f23), [sp]+
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lfm.w (f24 - f31), [sp]+
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ldm.w (r4), [sp]+
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ctf r4, s31
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#endif
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ldm.w (r4 - r15), [sp]+ @ restore registers from stack
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ldm.w (r16 - r27, pc), [sp]+ @ return to caller
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