65 lines
2.6 KiB
C
65 lines
2.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Derived from include/asm-x86/mach-summit/mach_mpparse.h
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* and include/asm-x86/mach-default/bios_ebda.h
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*
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* Author: Laurent Vivier <Laurent.Vivier@bull.net>
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*/
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#ifndef _ASM_X86_RIO_H
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#define _ASM_X86_RIO_H
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#define RIO_TABLE_VERSION 3
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struct rio_table_hdr {
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u8 version; /* Version number of this data structure */
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u8 num_scal_dev; /* # of Scalability devices */
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u8 num_rio_dev; /* # of RIO I/O devices */
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} __attribute__((packed));
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struct scal_detail {
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u8 node_id; /* Scalability Node ID */
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u32 CBAR; /* Address of 1MB register space */
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u8 port0node; /* Node ID port connected to: 0xFF=None */
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u8 port0port; /* Port num port connected to: 0,1,2, or */
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/* 0xFF=None */
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u8 port1node; /* Node ID port connected to: 0xFF = None */
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u8 port1port; /* Port num port connected to: 0,1,2, or */
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/* 0xFF=None */
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u8 port2node; /* Node ID port connected to: 0xFF = None */
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u8 port2port; /* Port num port connected to: 0,1,2, or */
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/* 0xFF=None */
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u8 chassis_num; /* 1 based Chassis number (1 = boot node) */
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} __attribute__((packed));
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struct rio_detail {
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u8 node_id; /* RIO Node ID */
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u32 BBAR; /* Address of 1MB register space */
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u8 type; /* Type of device */
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u8 owner_id; /* Node ID of Hurricane that owns this */
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/* node */
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u8 port0node; /* Node ID port connected to: 0xFF=None */
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u8 port0port; /* Port num port connected to: 0,1,2, or */
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/* 0xFF=None */
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u8 port1node; /* Node ID port connected to: 0xFF=None */
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u8 port1port; /* Port num port connected to: 0,1,2, or */
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/* 0xFF=None */
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u8 first_slot; /* Lowest slot number below this Calgary */
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u8 status; /* Bit 0 = 1 : the XAPIC is used */
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/* = 0 : the XAPIC is not used, ie: */
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/* ints fwded to another XAPIC */
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/* Bits1:7 Reserved */
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u8 WP_index; /* instance index - lower ones have */
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/* lower slot numbers/PCI bus numbers */
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u8 chassis_num; /* 1 based Chassis number */
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} __attribute__((packed));
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enum {
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HURR_SCALABILTY = 0, /* Hurricane Scalability info */
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HURR_RIOIB = 2, /* Hurricane RIOIB info */
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COMPAT_CALGARY = 4, /* Compatibility Calgary */
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ALT_CALGARY = 5, /* Second Planar Calgary */
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};
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#endif /* _ASM_X86_RIO_H */
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