439 lines
9.6 KiB
C
439 lines
9.6 KiB
C
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/*
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* Sony CXD2820R demodulator driver
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*
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* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "cxd2820r_priv.h"
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int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret, bw_i;
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unsigned int utmp;
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u32 if_frequency;
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u8 buf[3], bw_param;
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u8 bw_params1[][5] = {
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{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
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{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
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{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
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};
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u8 bw_params2[][2] = {
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{ 0x1f, 0xdc }, /* 6 MHz */
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{ 0x12, 0xf8 }, /* 7 MHz */
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{ 0x01, 0xe0 }, /* 8 MHz */
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};
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struct reg_val_mask tab[] = {
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{ 0x00080, 0x00, 0xff },
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{ 0x00081, 0x03, 0xff },
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{ 0x00085, 0x07, 0xff },
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{ 0x00088, 0x01, 0xff },
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{ 0x00070, priv->ts_mode, 0xff },
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{ 0x00071, !priv->ts_clk_inv << 4, 0x10 },
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{ 0x000cb, priv->if_agc_polarity << 6, 0x40 },
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{ 0x000a5, 0x00, 0x01 },
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{ 0x00082, 0x20, 0x60 },
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{ 0x000c2, 0xc3, 0xff },
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{ 0x0016a, 0x50, 0xff },
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{ 0x00427, 0x41, 0xff },
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};
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dev_dbg(&client->dev,
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"delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
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c->delivery_system, c->modulation, c->frequency,
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c->bandwidth_hz, c->inversion);
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switch (c->bandwidth_hz) {
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case 6000000:
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bw_i = 0;
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bw_param = 2;
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break;
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case 7000000:
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bw_i = 1;
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bw_param = 1;
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break;
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case 8000000:
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bw_i = 2;
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bw_param = 0;
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break;
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default:
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return -EINVAL;
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}
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/* program tuner */
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if (fe->ops.tuner_ops.set_params)
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fe->ops.tuner_ops.set_params(fe);
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if (priv->delivery_system != SYS_DVBT) {
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ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
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if (ret)
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goto error;
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}
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priv->delivery_system = SYS_DVBT;
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priv->ber_running = false; /* tune stops BER counter */
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/* program IF frequency */
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if (fe->ops.tuner_ops.get_if_frequency) {
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ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
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if (ret)
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goto error;
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dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
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} else {
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ret = -EINVAL;
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goto error;
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}
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utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
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buf[0] = (utmp >> 16) & 0xff;
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buf[1] = (utmp >> 8) & 0xff;
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buf[2] = (utmp >> 0) & 0xff;
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ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
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if (ret)
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goto error;
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ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
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if (ret)
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goto error;
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ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
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if (ret)
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goto error;
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ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
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if (ret)
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goto error;
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ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
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if (ret)
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goto error;
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ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
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if (ret)
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goto error;
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
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struct dtv_frontend_properties *c)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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int ret;
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unsigned int utmp;
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u8 buf[2];
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dev_dbg(&client->dev, "\n");
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ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
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if (ret)
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goto error;
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switch ((buf[0] >> 6) & 0x03) {
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case 0:
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c->modulation = QPSK;
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break;
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case 1:
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c->modulation = QAM_16;
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break;
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case 2:
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c->modulation = QAM_64;
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break;
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}
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switch ((buf[1] >> 1) & 0x03) {
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case 0:
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c->transmission_mode = TRANSMISSION_MODE_2K;
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break;
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case 1:
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c->transmission_mode = TRANSMISSION_MODE_8K;
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break;
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}
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switch ((buf[1] >> 3) & 0x03) {
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case 0:
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c->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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c->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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c->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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c->guard_interval = GUARD_INTERVAL_1_4;
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break;
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}
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switch ((buf[0] >> 3) & 0x07) {
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case 0:
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c->hierarchy = HIERARCHY_NONE;
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break;
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case 1:
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c->hierarchy = HIERARCHY_1;
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break;
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case 2:
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c->hierarchy = HIERARCHY_2;
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break;
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case 3:
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c->hierarchy = HIERARCHY_4;
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break;
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}
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switch ((buf[0] >> 0) & 0x07) {
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case 0:
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c->code_rate_HP = FEC_1_2;
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break;
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case 1:
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c->code_rate_HP = FEC_2_3;
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break;
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case 2:
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c->code_rate_HP = FEC_3_4;
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break;
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case 3:
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c->code_rate_HP = FEC_5_6;
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break;
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case 4:
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c->code_rate_HP = FEC_7_8;
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break;
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}
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switch ((buf[1] >> 5) & 0x07) {
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case 0:
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c->code_rate_LP = FEC_1_2;
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break;
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case 1:
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c->code_rate_LP = FEC_2_3;
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break;
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case 2:
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c->code_rate_LP = FEC_3_4;
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break;
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case 3:
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c->code_rate_LP = FEC_5_6;
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break;
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case 4:
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c->code_rate_LP = FEC_7_8;
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break;
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}
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ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
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if (ret)
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goto error;
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switch ((utmp >> 0) & 0x01) {
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case 0:
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c->inversion = INVERSION_OFF;
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break;
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case 1:
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c->inversion = INVERSION_ON;
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break;
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}
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return ret;
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error:
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dev_dbg(&client->dev, "failed=%d\n", ret);
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return ret;
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}
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int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct i2c_client *client = priv->client[0];
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret;
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unsigned int utmp, utmp1, utmp2;
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u8 buf[3];
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/* Lock detection */
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ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
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if (ret)
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goto error;
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ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
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if (ret)
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goto error;
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utmp1 = (buf[0] >> 0) & 0x07;
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utmp2 = (buf[1] >> 3) & 0x01;
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if (utmp1 == 6 && utmp2 == 1) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
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} else if (utmp1 == 6 || utmp2 == 1) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC;
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} else {
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*status = 0;
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}
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dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
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*status, 2, buf, utmp1, utmp2);
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/* Signal strength */
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if (*status & FE_HAS_SIGNAL) {
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unsigned int strength;
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ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
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if (ret)
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goto error;
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utmp = buf[0] << 8 | buf[1] << 0;
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utmp = ~utmp & 0x0fff;
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/* Scale value to 0x0000-0xffff */
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strength = utmp << 4 | utmp >> 8;
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c->strength.len = 1;
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c->strength.stat[0].scale = FE_SCALE_RELATIVE;
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c->strength.stat[0].uvalue = strength;
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} else {
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c->strength.len = 1;
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c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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/* CNR */
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if (*status & FE_HAS_VITERBI) {
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unsigned int cnr;
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ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
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if (ret)
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goto error;
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utmp = buf[0] << 8 | buf[1] << 0;
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if (utmp)
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cnr = div_u64((u64)(intlog10(utmp)
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- intlog10(32000 - utmp) + 55532585)
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* 10000, (1 << 24));
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else
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cnr = 0;
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c->cnr.len = 1;
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c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
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c->cnr.stat[0].svalue = cnr;
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} else {
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c->cnr.len = 1;
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c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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}
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/* BER */
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if (*status & FE_HAS_SYNC) {
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unsigned int post_bit_error;
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bool start_ber;
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if (priv->ber_running) {
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ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
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if (ret)
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goto error;
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if ((buf[2] >> 7) & 0x01) {
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post_bit_error = buf[2] << 16 | buf[1] << 8 |
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buf[0] << 0;
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post_bit_error &= 0x0fffff;
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start_ber = true;
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} else {
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post_bit_error = 0;
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start_ber = false;
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}
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} else {
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post_bit_error = 0;
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start_ber = true;
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}
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if (start_ber) {
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ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
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if (ret)
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goto error;
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priv->ber_running = true;
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}
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priv->post_bit_error += post_bit_error;
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c->post_bit_error.len = 1;
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|
|
c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
|
||
|
|
c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
|
||
|
|
} else {
|
||
|
|
c->post_bit_error.len = 1;
|
||
|
|
c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
error:
|
||
|
|
dev_dbg(&client->dev, "failed=%d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int cxd2820r_init_t(struct dvb_frontend *fe)
|
||
|
|
{
|
||
|
|
struct cxd2820r_priv *priv = fe->demodulator_priv;
|
||
|
|
struct i2c_client *client = priv->client[0];
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
dev_dbg(&client->dev, "\n");
|
||
|
|
|
||
|
|
ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
|
||
|
|
if (ret)
|
||
|
|
goto error;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
error:
|
||
|
|
dev_dbg(&client->dev, "failed=%d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int cxd2820r_sleep_t(struct dvb_frontend *fe)
|
||
|
|
{
|
||
|
|
struct cxd2820r_priv *priv = fe->demodulator_priv;
|
||
|
|
struct i2c_client *client = priv->client[0];
|
||
|
|
int ret;
|
||
|
|
struct reg_val_mask tab[] = {
|
||
|
|
{ 0x000ff, 0x1f, 0xff },
|
||
|
|
{ 0x00085, 0x00, 0xff },
|
||
|
|
{ 0x00088, 0x01, 0xff },
|
||
|
|
{ 0x00081, 0x00, 0xff },
|
||
|
|
{ 0x00080, 0x00, 0xff },
|
||
|
|
};
|
||
|
|
|
||
|
|
dev_dbg(&client->dev, "\n");
|
||
|
|
|
||
|
|
priv->delivery_system = SYS_UNDEFINED;
|
||
|
|
|
||
|
|
ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
|
||
|
|
if (ret)
|
||
|
|
goto error;
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
error:
|
||
|
|
dev_dbg(&client->dev, "failed=%d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
|
||
|
|
struct dvb_frontend_tune_settings *s)
|
||
|
|
{
|
||
|
|
s->min_delay_ms = 500;
|
||
|
|
s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
|
||
|
|
s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|