233 lines
6.7 KiB
C
233 lines
6.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MDP_ENGINE_H__
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#define __MDP_ENGINE_H__
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enum CMDQ_ENG_ENUM {
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/* ISP */
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CMDQ_ENG_WPEI = 0,
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CMDQ_ENG_WPEO, /* 1 */
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CMDQ_ENG_WPEI2, /* 2 */
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CMDQ_ENG_WPEO2, /* 3 */
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CMDQ_ENG_ISP_IMGI, /* 4 */
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CMDQ_ENG_ISP_IMGI2, /* 5 */
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CMDQ_ENG_ISP_IMG2O, /* 6 */
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CMDQ_ENG_ISP_IMG2O2, /* 7 */
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/* MDP */
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CMDQ_ENG_MDP_CAMIN, /* 8 */
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CMDQ_ENG_MDP_CAMIN2, /* 9 */
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CMDQ_ENG_MDP_CAMIN3, /* 10 */
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CMDQ_ENG_MDP_CAMIN4, /* 11 */
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CMDQ_ENG_MDP_RDMA0, /* 12 */
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CMDQ_ENG_MDP_RDMA1, /* 13 */
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CMDQ_ENG_MDP_RDMA2, /* 14 */
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CMDQ_ENG_MDP_RDMA3, /* 15 */
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CMDQ_ENG_MDP_FG0, /* 16 */
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CMDQ_ENG_MDP_FG1, /* 17 */
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CMDQ_ENG_MDP_PQ0_SOUT, /* 18 */
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CMDQ_ENG_MDP_PQ1_SOUT, /* 19 */
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CMDQ_ENG_MDP_HDR0, /* 20 */
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CMDQ_ENG_MDP_HDR1, /* 21 */
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CMDQ_ENG_MDP_COLOR0, /* 22 */
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CMDQ_ENG_MDP_COLOR1, /* 23 */
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CMDQ_ENG_MDP_AAL0, /* 24 */
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CMDQ_ENG_MDP_AAL1, /* 25 */
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CMDQ_ENG_MDP_AAL2, /* 26 */
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CMDQ_ENG_MDP_AAL3, /* 27 */
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CMDQ_ENG_MDP_RSZ0, /* 28 */
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CMDQ_ENG_MDP_RSZ1, /* 29 */
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CMDQ_ENG_MDP_RSZ2, /* 30 */
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CMDQ_ENG_MDP_RSZ3, /* 31 */
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CMDQ_ENG_MDP_TDSHP0, /* 32 */
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CMDQ_ENG_MDP_TDSHP1, /* 33 */
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CMDQ_ENG_MDP_TDSHP2, /* 34 */
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CMDQ_ENG_MDP_TDSHP3, /* 35 */
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CMDQ_ENG_MDP_TCC0, /* 36 */
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CMDQ_ENG_MDP_TCC1, /* 37 */
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CMDQ_ENG_MDP_TCC2, /* 38 */
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CMDQ_ENG_MDP_TCC3, /* 39 */
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CMDQ_ENG_MDP_WROT0, /* 40 */
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CMDQ_ENG_MDP_WROT1, /* 41 */
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CMDQ_ENG_MDP_WROT2, /* 42 */
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CMDQ_ENG_MDP_WROT3, /* 43 */
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/* DPE */
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CMDQ_ENG_DPE, /* 44 */
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CMDQ_ENG_RSC, /* 45 */
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CMDQ_ENG_GEPF, /* 46 */
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CMDQ_ENG_EAF, /* 47 */
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CMDQ_ENG_OWE, /* 48 */
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CMDQ_ENG_MFB, /* 49 */
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CMDQ_ENG_FDVT, /* 50 */
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/* ISP sec */
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CMDQ_ENG_ISP_VIPI, /* 51 */
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CMDQ_ENG_ISP_LCEI, /* 52 */
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CMDQ_ENG_ISP_IMG3O, /* 53 */
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CMDQ_ENG_ISP_SMXIO, /* 54 */
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CMDQ_ENG_ISP_DMGI_DEPI, /* 55 */
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CMDQ_ENG_ISP_IMGCI, /* 56 */
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CMDQ_ENG_ISP_UFBCI, /* 57 */
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CMDQ_ENG_ISP_UFBCO, /* 58 */
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CMDQ_ENG_ISP_MSS, /* 59 */
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CMDQ_ENG_ISP_MSF, /* 60 */
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CMDQ_ENG_INORDER, /* 61 */
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/* Dummy Engine */
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CMDQ_ENG_ISP_TIMGO = 63,
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CMDQ_ENG_MDP_WDMA = 63,
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CMDQ_MAX_ENGINE_COUNT /* ALWAYS keep at the end */
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};
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#define CMDQ_ENG_WPE_GROUP_BITS ((1LL << CMDQ_ENG_WPEI) | \
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(1LL << CMDQ_ENG_WPEO) | \
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(1LL << CMDQ_ENG_WPEI2) | \
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(1LL << CMDQ_ENG_WPEO2))
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#define CMDQ_ENG_ISP_GROUP_BITS ((1LL << CMDQ_ENG_ISP_IMGI) | \
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(1LL << CMDQ_ENG_ISP_IMGI2) | \
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(1LL << CMDQ_ENG_ISP_IMG2O) | \
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(1LL << CMDQ_ENG_ISP_IMG2O2))
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#define CMDQ_ENG_ISP_MTEE_GROUP_BITS ((1LL << CMDQ_ENG_ISP_IMGI) | \
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(1LL << CMDQ_ENG_ISP_VIPI) | \
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(1LL << CMDQ_ENG_ISP_LCEI))
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#define CMDQ_ENG_SVP_MTEE_GROUP_BITS ((1LL << CMDQ_ENG_MDP_RDMA0) | \
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(1LL << CMDQ_ENG_MDP_RDMA1) | \
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(1LL << CMDQ_ENG_MDP_RDMA2) | \
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(1LL << CMDQ_ENG_MDP_RDMA3))
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#define CMDQ_ENG_MTEE_GROUP_BITS ((1LL << CMDQ_ENG_ISP_IMGI) | \
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(1LL << CMDQ_ENG_ISP_VIPI) | \
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(1LL << CMDQ_ENG_ISP_LCEI))
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#define CMDQ_ENG_MDP_GROUP_BITS ((1LL << CMDQ_ENG_MDP_CAMIN) | \
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(1LL << CMDQ_ENG_MDP_CAMIN2) | \
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(1LL << CMDQ_ENG_MDP_CAMIN3) | \
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(1LL << CMDQ_ENG_MDP_CAMIN4) | \
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(1LL << CMDQ_ENG_MDP_RDMA0) | \
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(1LL << CMDQ_ENG_MDP_RDMA1) | \
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(1LL << CMDQ_ENG_MDP_RDMA2) | \
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(1LL << CMDQ_ENG_MDP_RDMA3) | \
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(1LL << CMDQ_ENG_MDP_RSZ0) | \
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(1LL << CMDQ_ENG_MDP_RSZ1) | \
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(1LL << CMDQ_ENG_MDP_RSZ2) | \
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(1LL << CMDQ_ENG_MDP_RSZ3) | \
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(1LL << CMDQ_ENG_MDP_TDSHP0) | \
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(1LL << CMDQ_ENG_MDP_TDSHP1) | \
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(1LL << CMDQ_ENG_MDP_TDSHP2) | \
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(1LL << CMDQ_ENG_MDP_TDSHP3) | \
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(1LL << CMDQ_ENG_MDP_COLOR0) | \
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(1LL << CMDQ_ENG_MDP_COLOR1) | \
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(1LL << CMDQ_ENG_MDP_WROT0) | \
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(1LL << CMDQ_ENG_MDP_WROT1) | \
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(1LL << CMDQ_ENG_MDP_WROT2) | \
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(1LL << CMDQ_ENG_MDP_WROT3) | \
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(1LL << CMDQ_ENG_MDP_AAL0) | \
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(1LL << CMDQ_ENG_MDP_AAL1) | \
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(1LL << CMDQ_ENG_MDP_AAL2) | \
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(1LL << CMDQ_ENG_MDP_AAL3) | \
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(1LL << CMDQ_ENG_MDP_TCC0) | \
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(1LL << CMDQ_ENG_MDP_TCC1) | \
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(1LL << CMDQ_ENG_MDP_TCC2) | \
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(1LL << CMDQ_ENG_MDP_TCC3) | \
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(1LL << CMDQ_ENG_MDP_FG0) | \
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(1LL << CMDQ_ENG_MDP_FG1) | \
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(1LL << CMDQ_ENG_MDP_HDR0) | \
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(1LL << CMDQ_ENG_MDP_HDR1))
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#define CMDQ_ENG_DPE_GROUP_BITS (1LL << CMDQ_ENG_DPE)
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#define CMDQ_ENG_RSC_GROUP_BITS (1LL << CMDQ_ENG_RSC)
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#define CMDQ_ENG_GEPF_GROUP_BITS (1LL << CMDQ_ENG_GEPF)
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#define CMDQ_ENG_EAF_GROUP_BITS (1LL << CMDQ_ENG_EAF)
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#define CMDQ_ENG_OWE_GROUP_BITS (1LL << CMDQ_ENG_OWE)
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#define CMDQ_ENG_MFB_GROUP_BITS (1LL << CMDQ_ENG_MFB)
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#define CMDQ_ENG_FDVT_GROUP_BITS (1LL << CMDQ_ENG_FDVT)
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#define CMDQ_ENG_ISP_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_ISP_GROUP_BITS))
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#define CMDQ_ENG_MDP_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_MDP_GROUP_BITS))
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#define CMDQ_ENG_DPE_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_DPE_GROUP_BITS))
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#define CMDQ_ENG_RSC_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_RSC_GROUP_BITS))
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#define CMDQ_ENG_GEPF_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_GEPF_GROUP_BITS))
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#define CMDQ_ENG_WPE_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_WPE_GROUP_BITS))
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#define CMDQ_ENG_EAF_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_EAF_GROUP_BITS))
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#define CMDQ_ENG_OWE_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_OWE_GROUP_BITS))
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#define CMDQ_ENG_MFB_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_MFB_GROUP_BITS))
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#define CMDQ_ENG_FDVT_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_FDVT_GROUP_BITS))
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#define CMDQ_FOREACH_GROUP(ACTION_struct)\
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ACTION_struct(CMDQ_GROUP_ISP, ISP) \
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ACTION_struct(CMDQ_GROUP_MDP, MDP) \
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ACTION_struct(CMDQ_GROUP_DPE, DPE) \
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ACTION_struct(CMDQ_GROUP_RSC, RSC) \
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ACTION_struct(CMDQ_GROUP_GEPF, GEPF) \
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ACTION_struct(CMDQ_GROUP_WPE, WPE) \
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ACTION_struct(CMDQ_GROUP_EAF, EAF) \
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ACTION_struct(CMDQ_GROUP_OWE, OWE) \
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ACTION_struct(CMDQ_GROUP_MFB, MFB) \
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ACTION_struct(CMDQ_GROUP_FDVT, FDVT)
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#define MDP_GENERATE_ENUM(_enum, _string) _enum,
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enum CMDQ_GROUP_ENUM {
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CMDQ_FOREACH_GROUP(MDP_GENERATE_ENUM)
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CMDQ_MAX_GROUP_COUNT, /* ALWAYS keep at the end */
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};
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enum MDP_ENG_BASE {
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ENGBASE_MMSYS_CONFIG = 0,
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ENGBASE_MDP_RDMA0,
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ENGBASE_MDP_RDMA1,
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ENGBASE_MDP_RDMA2,
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ENGBASE_MDP_RDMA3,
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ENGBASE_MDP_FG0,
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ENGBASE_MDP_FG1,
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ENGBASE_MDP_AAL0,
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ENGBASE_MDP_AAL1,
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ENGBASE_MDP_AAL2,
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ENGBASE_MDP_AAL3,
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ENGBASE_MDP_HDR0,
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ENGBASE_MDP_HDR1,
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ENGBASE_MDP_RSZ0,
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ENGBASE_MDP_RSZ1,
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ENGBASE_MDP_RSZ2,
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ENGBASE_MDP_RSZ3,
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ENGBASE_MDP_WROT0,
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ENGBASE_MDP_WROT1,
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ENGBASE_MDP_WROT2,
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ENGBASE_MDP_WROT3,
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ENGBASE_MDP_TDSHP0,
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ENGBASE_MDP_TDSHP1,
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ENGBASE_MDP_TDSHP2,
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ENGBASE_MDP_TDSHP3,
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ENGBASE_MDP_TCC0,
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ENGBASE_MDP_TCC1,
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ENGBASE_MDP_TCC2,
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ENGBASE_MDP_TCC3,
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ENGBASE_MDP_COLOR0,
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ENGBASE_MDP_COLOR1,
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ENGBASE_MMSYS_MUTEX,
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ENGBASE_ISP_MSFDL,
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ENGBASE_ISP_MSS,
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ENGBASE_ISP_MFB,
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ENGBASE_ISP_DIP_A0,
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ENGBASE_ISP_DIP_A1,
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ENGBASE_ISP_DIP_A7,
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ENGBASE_IMGSYS2_CONFIG,
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ENGBASE_ISP_DIP_B0,
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ENGBASE_ISP_DIP_B1,
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ENGBASE_ISP_DIP_B7,
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ENGBASE_ISP_WPE_A,
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ENGBASE_ISP_WPE_B,
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ENGBASE_COUNT
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};
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#endif /* __MDP_ENGINE_H__ */
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