229 lines
7.6 KiB
C
229 lines
7.6 KiB
C
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/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#include "iwl-trans.h"
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#include "iwl-fh.h"
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#include "iwl-context-info-gen3.h"
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#include "internal.h"
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#include "iwl-prph.h"
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int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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const struct fw_img *fw)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_context_info_gen3 *ctxt_info_gen3;
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struct iwl_prph_scratch *prph_scratch;
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struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
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struct iwl_prph_info *prph_info;
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void *iml_img;
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u32 control_flags = 0;
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int ret;
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/* Allocate prph scratch */
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prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
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&trans_pcie->prph_scratch_dma_addr,
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GFP_KERNEL);
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if (!prph_scratch)
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return -ENOMEM;
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prph_sc_ctrl = &prph_scratch->ctrl_cfg;
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prph_sc_ctrl->version.version = 0;
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prph_sc_ctrl->version.mac_id =
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cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
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prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
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control_flags = IWL_PRPH_SCRATCH_RB_SIZE_4K |
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IWL_PRPH_SCRATCH_MTR_MODE |
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(IWL_PRPH_MTR_FORMAT_256B &
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IWL_PRPH_SCRATCH_MTR_FORMAT) |
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IWL_PRPH_SCRATCH_EARLY_DEBUG_EN |
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IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
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prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
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/* initialize RX default queue */
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prph_sc_ctrl->rbd_cfg.free_rbd_addr =
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cpu_to_le64(trans_pcie->rxq->bd_dma);
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/* Configure debug, for integration */
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iwl_pcie_alloc_fw_monitor(trans, 0);
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prph_sc_ctrl->hwm_cfg.hwm_base_addr =
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cpu_to_le64(trans_pcie->fw_mon_phys);
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prph_sc_ctrl->hwm_cfg.hwm_size =
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cpu_to_le32(trans_pcie->fw_mon_size);
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/* allocate ucode sections in dram and set addresses */
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ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
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if (ret)
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goto err_free_prph_scratch;
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/* Allocate prph information
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* currently we don't assign to the prph info anything, but it would get
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* assigned later */
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prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
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&trans_pcie->prph_info_dma_addr,
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GFP_KERNEL);
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if (!prph_info) {
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ret = -ENOMEM;
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goto err_free_prph_scratch;
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}
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/* Allocate context info */
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ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
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sizeof(*ctxt_info_gen3),
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&trans_pcie->ctxt_info_dma_addr,
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GFP_KERNEL);
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if (!ctxt_info_gen3) {
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ret = -ENOMEM;
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goto err_free_prph_info;
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}
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ctxt_info_gen3->prph_info_base_addr =
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cpu_to_le64(trans_pcie->prph_info_dma_addr);
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ctxt_info_gen3->prph_scratch_base_addr =
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cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
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ctxt_info_gen3->prph_scratch_size =
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cpu_to_le32(sizeof(*prph_scratch));
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ctxt_info_gen3->cr_head_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
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ctxt_info_gen3->tr_tail_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
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ctxt_info_gen3->cr_tail_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
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ctxt_info_gen3->cr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
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ctxt_info_gen3->tr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
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ctxt_info_gen3->mtr_base_addr =
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cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
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ctxt_info_gen3->mcr_base_addr =
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cpu_to_le64(trans_pcie->rxq->used_bd_dma);
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ctxt_info_gen3->mtr_size =
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cpu_to_le16(TFD_QUEUE_CB_SIZE(TFD_CMD_SLOTS));
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ctxt_info_gen3->mcr_size =
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cpu_to_le16(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE));
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trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
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trans_pcie->prph_info = prph_info;
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trans_pcie->prph_scratch = prph_scratch;
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/* Allocate IML */
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iml_img = dma_alloc_coherent(trans->dev, trans->iml_len,
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&trans_pcie->iml_dma_addr, GFP_KERNEL);
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if (!iml_img) {
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ret = -ENOMEM;
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goto err_free_ctxt_info;
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}
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memcpy(iml_img, trans->iml, trans->iml_len);
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iwl_enable_fw_load_int_ctx_info(trans);
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/* kick FW self load */
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iwl_write64(trans, CSR_CTXT_INFO_ADDR,
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trans_pcie->ctxt_info_dma_addr);
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iwl_write64(trans, CSR_IML_DATA_ADDR,
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trans_pcie->iml_dma_addr);
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iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
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iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL, CSR_AUTO_FUNC_BOOT_ENA);
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iwl_set_bit(trans, CSR_GP_CNTRL, CSR_AUTO_FUNC_INIT);
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return 0;
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err_free_ctxt_info:
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
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trans_pcie->ctxt_info_gen3,
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trans_pcie->ctxt_info_dma_addr);
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trans_pcie->ctxt_info_gen3 = NULL;
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err_free_prph_info:
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dma_free_coherent(trans->dev,
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sizeof(*prph_info),
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prph_info,
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trans_pcie->prph_info_dma_addr);
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err_free_prph_scratch:
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dma_free_coherent(trans->dev,
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sizeof(*prph_scratch),
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prph_scratch,
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trans_pcie->prph_scratch_dma_addr);
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return ret;
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}
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void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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if (!trans_pcie->ctxt_info_gen3)
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return;
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
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trans_pcie->ctxt_info_gen3,
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trans_pcie->ctxt_info_dma_addr);
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trans_pcie->ctxt_info_dma_addr = 0;
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trans_pcie->ctxt_info_gen3 = NULL;
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iwl_pcie_ctxt_info_free_fw_img(trans);
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
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trans_pcie->prph_scratch,
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trans_pcie->prph_scratch_dma_addr);
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trans_pcie->prph_scratch_dma_addr = 0;
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trans_pcie->prph_scratch = NULL;
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
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trans_pcie->prph_info,
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trans_pcie->prph_info_dma_addr);
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trans_pcie->prph_info_dma_addr = 0;
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trans_pcie->prph_info = NULL;
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}
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