681 lines
18 KiB
C
681 lines
18 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_CLK_MT6853_H
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#define _DT_BINDINGS_CLK_MT6853_H
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL_LL 0
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#define CLK_APMIXED_ARMPLL_BL0 1
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#define CLK_APMIXED_CCIPLL 2
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#define CLK_APMIXED_MPLL 3
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#define CLK_APMIXED_MAINPLL 4
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#define CLK_APMIXED_UNIVPLL 5
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#define CLK_APMIXED_MSDCPLL 6
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#define CLK_APMIXED_MMPLL 7
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#define CLK_APMIXED_ADSPPLL 8
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#define CLK_APMIXED_MFGPLL 9
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#define CLK_APMIXED_TVDPLL 10
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#define CLK_APMIXED_APLL1 11
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#define CLK_APMIXED_APLL2 12
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#define CLK_APMIXED_NPUPLL 13
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#define CLK_APMIXED_USBPLL 14
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#define CLK_APMIXED_PLL_MIPIC0_26M_EN 15
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#define CLK_APMIXED_PLL_MIPIC1_26M_EN 16
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#define CLK_APMIXED_PLL_MIPID0_26M_EN 17
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#define CLK_APMIXED_NR_CLK 18
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/* TOPCKGEN */
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#define CLK_TOP_MAINPLL 0
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#define CLK_TOP_MAINPLL_D3 1
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#define CLK_TOP_MAINPLL_D4 2
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#define CLK_TOP_MAINPLL_D4_D2 3
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#define CLK_TOP_MAINPLL_D4_D4 4
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#define CLK_TOP_MAINPLL_D4_D8 5
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#define CLK_TOP_MAINPLL_D4_D16 6
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#define CLK_TOP_MAINPLL_D5 7
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#define CLK_TOP_MAINPLL_D5_D2 8
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#define CLK_TOP_MAINPLL_D5_D4 9
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#define CLK_TOP_MAINPLL_D5_D8 10
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#define CLK_TOP_MAINPLL_D6 11
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#define CLK_TOP_MAINPLL_D6_D2 12
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#define CLK_TOP_MAINPLL_D6_D4 13
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#define CLK_TOP_MAINPLL_D6_D8 14
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#define CLK_TOP_MAINPLL_D7 15
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#define CLK_TOP_MAINPLL_D7_D2 16
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#define CLK_TOP_MAINPLL_D7_D4 17
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#define CLK_TOP_MAINPLL_D7_D8 18
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#define CLK_TOP_MAINPLL_D9 19
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#define CLK_TOP_UNIVPLL_192M 20
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#define CLK_TOP_UNIVPLL_192M_D2 21
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#define CLK_TOP_UNIVPLL_192M_D4 22
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#define CLK_TOP_UNIVPLL_192M_D8 23
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#define CLK_TOP_UNIVPLL_192M_D16 24
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#define CLK_TOP_UNIVPLL_192M_D32 25
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#define CLK_TOP_UNIVPLL 26
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#define CLK_TOP_UNIVPLL_D2 27
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#define CLK_TOP_UNIVPLL_D3 28
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#define CLK_TOP_UNIVPLL_D4 29
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#define CLK_TOP_UNIVPLL_D4_D2 30
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#define CLK_TOP_UNIVPLL_D4_D4 31
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#define CLK_TOP_UNIVPLL_D4_D8 32
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#define CLK_TOP_UNIVPLL_D5 33
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#define CLK_TOP_UNIVPLL_D5_D2 34
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#define CLK_TOP_UNIVPLL_D5_D4 35
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#define CLK_TOP_UNIVPLL_D5_D8 36
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#define CLK_TOP_UNIVPLL_D5_D16 37
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#define CLK_TOP_UNIVPLL_D6 38
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#define CLK_TOP_UNIVPLL_D6_D2 39
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#define CLK_TOP_UNIVPLL_D6_D4 40
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#define CLK_TOP_UNIVPLL_D6_D8 41
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#define CLK_TOP_UNIVPLL_D6_D16 42
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#define CLK_TOP_UNIVPLL_D7 43
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#define CLK_TOP_UNIVPLL_D7_D2 44
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#define CLK_TOP_MFGPLL 45
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#define CLK_TOP_APLL1 46
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#define CLK_TOP_APLL1_D2 47
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#define CLK_TOP_APLL1_D4 48
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#define CLK_TOP_APLL1_D8 49
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#define CLK_TOP_APLL2 50
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#define CLK_TOP_APLL2_D2 51
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#define CLK_TOP_APLL2_D4 52
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#define CLK_TOP_APLL2_D8 53
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#define CLK_TOP_ADSPPLL 54
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#define CLK_TOP_MMPLL_D3 55
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#define CLK_TOP_MMPLL_D4 56
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#define CLK_TOP_MMPLL_D4_D2 57
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#define CLK_TOP_MMPLL_D4_D4 58
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#define CLK_TOP_MMPLL_D5 59
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#define CLK_TOP_MMPLL_D5_D2 60
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#define CLK_TOP_MMPLL_D5_D4 61
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#define CLK_TOP_MMPLL_D6 62
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#define CLK_TOP_MMPLL_D6_D2 63
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#define CLK_TOP_MMPLL_D7 64
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#define CLK_TOP_MMPLL_D9 65
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#define CLK_TOP_NPUPLL 66
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#define CLK_TOP_TVDPLL 67
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#define CLK_TOP_TVDPLL_D2 68
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#define CLK_TOP_TVDPLL_D4 69
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#define CLK_TOP_TVDPLL_D8 70
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#define CLK_TOP_TVDPLL_D16 71
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#define CLK_TOP_MSDCPLL 72
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#define CLK_TOP_MSDCPLL_D2 73
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#define CLK_TOP_MSDCPLL_D4 74
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#define CLK_TOP_MSDCPLL_D8 75
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#define CLK_TOP_MSDCPLL_D16 76
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#define CLK_TOP_OSC 77
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#define CLK_TOP_OSC_D2 78
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#define CLK_TOP_OSC_D4 79
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#define CLK_TOP_OSC_D8 80
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#define CLK_TOP_OSC_D16 81
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#define CLK_TOP_OSC_D10 82
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#define CLK_TOP_OSC_D20 83
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#define CLK_TOP_OSC_CK_2 84
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#define CLK_TOP_OSC2_D2 85
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#define CLK_TOP_TCK_26M_MX9 86
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#define CLK_TOP_CSW_F26M_CK_D2 87
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#define CLK_TOP_F26M 88
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#define CLK_TOP_FRTC 89
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#define CLK_TOP_AXI 90
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#define CLK_TOP_SPM 91
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#define CLK_TOP_SCP 92
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#define CLK_TOP_BUS 93
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#define CLK_TOP_DISP 94
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#define CLK_TOP_MDP 95
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#define CLK_TOP_IMG1 96
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#define CLK_TOP_IMG2 97
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#define CLK_TOP_IPE 98
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#define CLK_TOP_DPE 99
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#define CLK_TOP_CAM 100
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#define CLK_TOP_CCU 101
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#define CLK_TOP_DSP 102
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#define CLK_TOP_DSP1 103
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#define CLK_TOP_DSP2 104
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#define CLK_TOP_IPU_IF 105
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#define CLK_TOP_MFG_REF 106
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#define CLK_TOP_FCAMTG 107
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#define CLK_TOP_FCAMTG2 108
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#define CLK_TOP_FCAMTG3 109
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#define CLK_TOP_FCAMTG4 110
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#define CLK_TOP_FCAMTG5 111
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#define CLK_TOP_FUART 112
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#define CLK_TOP_SPI 113
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#define CLK_TOP_MSDC50_0_HCLK 114
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#define CLK_TOP_MSDC50_0 115
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#define CLK_TOP_MSDC30_1 116
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#define CLK_TOP_AUDIO 117
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#define CLK_TOP_AUD_INTBUS 118
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#define CLK_TOP_FPWRAP_ULPOSC 119
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#define CLK_TOP_ATB 120
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#define CLK_TOP_SSPM 121
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#define CLK_TOP_SCAM 122
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#define CLK_TOP_FDISP_PWM 123
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#define CLK_TOP_FUSB_TOP 124
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#define CLK_TOP_FSSUSB_XHCI 125
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#define CLK_TOP_I2C 126
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#define CLK_TOP_FSENINF 127
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#define CLK_TOP_FSENINF1 128
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#define CLK_TOP_FSENINF2 129
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#define CLK_TOP_DXCC 130
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#define CLK_TOP_AUD_ENGEN1 131
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#define CLK_TOP_AUD_ENGEN2 132
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#define CLK_TOP_AES_UFSFDE 133
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#define CLK_TOP_UFS 134
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#define CLK_TOP_AUD_1 135
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#define CLK_TOP_AUD_2 136
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#define CLK_TOP_ADSP 137
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#define CLK_TOP_DPMAIF_MAIN 138
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#define CLK_TOP_VENC 139
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#define CLK_TOP_VDEC 140
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#define CLK_TOP_CAMTM 141
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#define CLK_TOP_PWM 142
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#define CLK_TOP_AUDIO_H 143
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#define CLK_TOP_SPMI_MST 144
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#define CLK_TOP_DVFSRC 145
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#define CLK_TOP_AES_MSDCFDE 146
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#define CLK_TOP_MCUPM 147
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#define CLK_TOP_SFLASH 148
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#define CLK_TOP_DSI_OCC 149
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#define CLK_TOP_UNIPLL_SES 150
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#define CLK_TOP_I2C_PSEUDO 151
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#define CLK_TOP_APDMA_PSEUDO 152
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#define CLK_TOP_AXI_SEL 153
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#define CLK_TOP_SPM_SEL 154
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#define CLK_TOP_SCP_SEL 155
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#define CLK_TOP_BUS_AXIMEM_SEL 156
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#define CLK_TOP_DISP_SEL 157
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#define CLK_TOP_MDP_SEL 158
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#define CLK_TOP_IMG1_SEL 159
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#define CLK_TOP_IMG2_SEL 160
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#define CLK_TOP_IPE_SEL 161
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#define CLK_TOP_DPE_SEL 162
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#define CLK_TOP_CAM_SEL 163
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#define CLK_TOP_CCU_SEL 164
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#define CLK_TOP_DSP_SEL 165
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#define CLK_TOP_DSP1_SEL 166
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#define CLK_TOP_DSP1_NPUPLL_SEL 167
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#define CLK_TOP_DSP2_SEL 168
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#define CLK_TOP_DSP2_NPUPLL_SEL 169
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#define CLK_TOP_IPU_IF_SEL 170
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#define CLK_TOP_MFG_REF_SEL 171
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#define CLK_TOP_MFG_PLL_SEL 172
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#define CLK_TOP_CAMTG_SEL 173
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#define CLK_TOP_CAMTG2_SEL 174
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#define CLK_TOP_CAMTG3_SEL 175
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#define CLK_TOP_CAMTG4_SEL 176
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#define CLK_TOP_CAMTG5_SEL 177
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#define CLK_TOP_UART_SEL 178
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#define CLK_TOP_SPI_SEL 179
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#define CLK_TOP_MSDC50_0_HCLK_SEL 180
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#define CLK_TOP_MSDC50_0_SEL 181
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#define CLK_TOP_MSDC30_1_SEL 182
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#define CLK_TOP_AUDIO_SEL 183
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#define CLK_TOP_AUD_INTBUS_SEL 184
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#define CLK_TOP_PWRAP_ULPOSC_SEL 185
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#define CLK_TOP_ATB_SEL 186
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#define CLK_TOP_SSPM_SEL 187
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#define CLK_TOP_SCAM_SEL 188
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#define CLK_TOP_DISP_PWM_SEL 189
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#define CLK_TOP_USB_TOP_SEL 190
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#define CLK_TOP_SSUSB_XHCI_SEL 191
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#define CLK_TOP_I2C_SEL 192
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#define CLK_TOP_SENINF_SEL 193
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#define CLK_TOP_SENINF1_SEL 194
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#define CLK_TOP_SENINF2_SEL 195
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#define CLK_TOP_DXCC_SEL 196
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#define CLK_TOP_AUD_ENGEN1_SEL 197
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#define CLK_TOP_AUD_ENGEN2_SEL 198
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#define CLK_TOP_AES_UFSFDE_SEL 199
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#define CLK_TOP_UFS_SEL 200
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#define CLK_TOP_AUD_1_SEL 201
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#define CLK_TOP_AUD_2_SEL 202
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#define CLK_TOP_ADSP_SEL 203
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#define CLK_TOP_DPMAIF_MAIN_SEL 204
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#define CLK_TOP_VENC_SEL 205
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#define CLK_TOP_VDEC_SEL 206
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#define CLK_TOP_CAMTM_SEL 207
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#define CLK_TOP_PWM_SEL 208
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#define CLK_TOP_AUDIO_H_SEL 209
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#define CLK_TOP_SPMI_MST_SEL 210
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#define CLK_TOP_DVFSRC_SEL 211
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#define CLK_TOP_AES_MSDCFDE_SEL 212
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#define CLK_TOP_MCUPM_SEL 213
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#define CLK_TOP_SFLASH_SEL 214
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#define CLK_TOP_APLL_I2S0_MCK_SEL 215
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#define CLK_TOP_APLL_I2S1_MCK_SEL 216
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#define CLK_TOP_APLL_I2S2_MCK_SEL 217
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#define CLK_TOP_APLL_I2S3_MCK_SEL 218
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#define CLK_TOP_APLL_I2S4_MCK_SEL 219
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#define CLK_TOP_APLL_I2S5_MCK_SEL 220
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#define CLK_TOP_APLL_I2S6_MCK_SEL 221
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#define CLK_TOP_APLL_I2S7_MCK_SEL 222
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#define CLK_TOP_APLL_I2S8_MCK_SEL 223
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#define CLK_TOP_APLL_I2S9_MCK_SEL 224
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#define CLK_TOP_APLL12_CK_DIV0 225
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#define CLK_TOP_APLL12_CK_DIV1 226
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#define CLK_TOP_APLL12_CK_DIV2 227
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#define CLK_TOP_APLL12_CK_DIV3 228
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#define CLK_TOP_APLL12_CK_DIV4 229
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#define CLK_TOP_APLL12_CK_DIVB 230
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#define CLK_TOP_APLL12_CK_DIV5 231
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#define CLK_TOP_APLL12_CK_DIV6 232
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#define CLK_TOP_APLL12_CK_DIV7 233
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#define CLK_TOP_APLL12_CK_DIV8 234
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#define CLK_TOP_APLL12_CK_DIV9 235
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#define CLK_TOP_NR_CLK 236
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/* INFRACFG_AO */
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#define CLK_IFRAO_INFRA_DCM_RG_FORCE 0
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#define CLK_IFRAO_PMIC_TMR 1
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#define CLK_IFRAO_PMIC_AP 2
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#define CLK_IFRAO_PMIC_MD 3
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#define CLK_IFRAO_PMIC_CONN 4
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#define CLK_IFRAO_SEJ 5
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#define CLK_IFRAO_APXGPT 6
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#define CLK_IFRAO_GCE 7
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#define CLK_IFRAO_GCE2 8
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#define CLK_IFRAO_THERM 9
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#define CLK_IFRAO_I2C0 10
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#define CLK_IFRAO_I2C1 11
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#define CLK_IFRAO_I2C2 12
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#define CLK_IFRAO_I2C3 13
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#define CLK_IFRAO_PWM_HCLK 14
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#define CLK_IFRAO_PWM1 15
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#define CLK_IFRAO_PWM2 16
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#define CLK_IFRAO_PWM3 17
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#define CLK_IFRAO_PWM4 18
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#define CLK_IFRAO_PWM 19
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#define CLK_IFRAO_UART0 20
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#define CLK_IFRAO_UART1 21
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#define CLK_IFRAO_UART2 22
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#define CLK_IFRAO_UART3 23
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#define CLK_IFRAO_GCE_26M 24
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#define CLK_IFRAO_CQ_DMA_FPC 25
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#define CLK_IFRAO_BTIF 26
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#define CLK_IFRAO_SPI0 27
|
||
|
|
#define CLK_IFRAO_MSDC0 28
|
||
|
|
#define CLK_IFRAO_MSDC1 29
|
||
|
|
#define CLK_IFRAO_MSDC0_SRC 30
|
||
|
|
#define CLK_IFRAO_DVFSRC 31
|
||
|
|
#define CLK_IFRAO_TRNG 32
|
||
|
|
#define CLK_IFRAO_AUXADC 33
|
||
|
|
#define CLK_IFRAO_CPUM 34
|
||
|
|
#define CLK_IFRAO_CCIF1_AP 35
|
||
|
|
#define CLK_IFRAO_CCIF1_MD 36
|
||
|
|
#define CLK_IFRAO_AUXADC_MD 37
|
||
|
|
#define CLK_IFRAO_PCIE_TL_26M 38
|
||
|
|
#define CLK_IFRAO_MSDC1_SRC 39
|
||
|
|
#define CLK_IFRAO_MSDC0_AES 40
|
||
|
|
#define CLK_IFRAO_PCIE_TL_96M 41
|
||
|
|
#define CLK_IFRAO_PCIE_PL_PCLK_250M 42
|
||
|
|
#define CLK_IFRAO_DEVICE_APC 43
|
||
|
|
#define CLK_IFRAO_CCIF_AP 44
|
||
|
|
#define CLK_IFRAO_DEBUGSYS 45
|
||
|
|
#define CLK_IFRAO_AUDIO 46
|
||
|
|
#define CLK_IFRAO_CCIF_MD 47
|
||
|
|
#define CLK_IFRAO_DXCC_SEC_CORE 48
|
||
|
|
#define CLK_IFRAO_DXCC_AO 49
|
||
|
|
#define CLK_IFRAO_DBG_TRACE 50
|
||
|
|
#define CLK_IFRAO_DRAMC_F26M 51
|
||
|
|
#define CLK_IFRAO_SSUSB 52
|
||
|
|
#define CLK_IFRAO_DISP_PWM 53
|
||
|
|
#define CLK_IFRAO_CLDMA_BCLK 54
|
||
|
|
#define CLK_IFRAO_AUDIO_26M_BCLK 55
|
||
|
|
#define CLK_IFRAO_MODEM_TEMP_SHARE 56
|
||
|
|
#define CLK_IFRAO_SPI1 57
|
||
|
|
#define CLK_IFRAO_I2C4 58
|
||
|
|
#define CLK_IFRAO_SPI2 59
|
||
|
|
#define CLK_IFRAO_SPI3 60
|
||
|
|
#define CLK_IFRAO_UNIPRO_SYSCLK 61
|
||
|
|
#define CLK_IFRAO_UNIPRO_TICK 62
|
||
|
|
#define CLK_IFRAO_UFS_MP_SAP_BCLK 63
|
||
|
|
#define CLK_IFRAO_FSSPM 64
|
||
|
|
#define CLK_IFRAO_SSPM_BUS_HCLK 65
|
||
|
|
#define CLK_IFRAO_I2C5 66
|
||
|
|
#define CLK_IFRAO_I2C5_ARBITER 67
|
||
|
|
#define CLK_IFRAO_I2C5_IMM 68
|
||
|
|
#define CLK_IFRAO_I2C1_ARBITER 69
|
||
|
|
#define CLK_IFRAO_I2C1_IMM 70
|
||
|
|
#define CLK_IFRAO_I2C2_ARBITER 71
|
||
|
|
#define CLK_IFRAO_I2C2_IMM 72
|
||
|
|
#define CLK_IFRAO_SPI4 73
|
||
|
|
#define CLK_IFRAO_SPI5 74
|
||
|
|
#define CLK_IFRAO_CQ_DMA 75
|
||
|
|
#define CLK_IFRAO_UFS 76
|
||
|
|
#define CLK_IFRAO_AES 77
|
||
|
|
#define CLK_IFRAO_UFS_TICK 78
|
||
|
|
#define CLK_IFRAO_SSUSB_XHCI 79
|
||
|
|
#define CLK_IFRAO_MSDC0_SELF 80
|
||
|
|
#define CLK_IFRAO_MSDC1_SELF 81
|
||
|
|
#define CLK_IFRAO_MSDC2_SELF 82
|
||
|
|
#define CLK_IFRAO_SSPM_26M_SELF 83
|
||
|
|
#define CLK_IFRAO_SSPM_32K_SELF 84
|
||
|
|
#define CLK_IFRAO_I2C6 85
|
||
|
|
#define CLK_IFRAO_AP_MSDC0 86
|
||
|
|
#define CLK_IFRAO_MD_MSDC0 87
|
||
|
|
#define CLK_IFRAO_CCIF5_AP 88
|
||
|
|
#define CLK_IFRAO_CCIF5_MD 89
|
||
|
|
#define CLK_IFRAO_FLASHIF_TOP_HCLK_133M 90
|
||
|
|
#define CLK_IFRAO_CCIF2_AP 91
|
||
|
|
#define CLK_IFRAO_CCIF2_MD 92
|
||
|
|
#define CLK_IFRAO_CCIF3_AP 93
|
||
|
|
#define CLK_IFRAO_CCIF3_MD 94
|
||
|
|
#define CLK_IFRAO_SEJ_F13M 95
|
||
|
|
#define CLK_IFRAO_I2C7 96
|
||
|
|
#define CLK_IFRAO_I2C8 97
|
||
|
|
#define CLK_IFRAO_FBIST2FPC 98
|
||
|
|
#define CLK_IFRAO_DEVICE_APC_SYNC 99
|
||
|
|
#define CLK_IFRAO_DPMAIF_MAIN 100
|
||
|
|
#define CLK_IFRAO_CCIF4_AP 101
|
||
|
|
#define CLK_IFRAO_CCIF4_MD 102
|
||
|
|
#define CLK_IFRAO_SPI6_CK 103
|
||
|
|
#define CLK_IFRAO_SPI7_CK 104
|
||
|
|
#define CLK_IFRAO_133M_MCLK_CK 105
|
||
|
|
#define CLK_IFRAO_66M_MCLK_CK 106
|
||
|
|
#define CLK_IFRAO_66M_PERI_BUS_MCLK_CK 107
|
||
|
|
#define CLK_IFRAO_INFRA_FREE_DCM_133M 108
|
||
|
|
#define CLK_IFRAO_INFRA_FREE_DCM_66M 109
|
||
|
|
#define CLK_IFRAO_PERU_BUS_DCM_133M 110
|
||
|
|
#define CLK_IFRAO_PERU_BUS_DCM_66M 111
|
||
|
|
#define CLK_IFRAO_RG_FLASHIF_PERI_26M_CK 112
|
||
|
|
#define CLK_IFRAO_RG_FLASHIF_SFLASH_CK 113
|
||
|
|
#define CLK_IFRAO_AP_DMA 114
|
||
|
|
#define CLK_IFRAO_PERI_DCM_RG_FORCE 115
|
||
|
|
#define CLK_IFRAO_NR_CLK 116
|
||
|
|
|
||
|
|
/* PERICFG */
|
||
|
|
|
||
|
|
#define CLK_PERIAXI_DISABLE 0
|
||
|
|
#define CLK_PERI_NR_CLK 1
|
||
|
|
|
||
|
|
/* SCP */
|
||
|
|
|
||
|
|
#define CLK_SCP_PAR_ADSP_PLL 0
|
||
|
|
#define CLK_SCP_PAR_NR_CLK 1
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_C */
|
||
|
|
|
||
|
|
#define CLK_IMPC_AP_CLOCK_RO_I2C10 0
|
||
|
|
#define CLK_IMPC_AP_CLOCK_RO_I2C11 1
|
||
|
|
#define CLK_IMPC_NR_CLK 2
|
||
|
|
|
||
|
|
/* AUDIO */
|
||
|
|
|
||
|
|
#define CLK_AUDSYS_AFE 0
|
||
|
|
#define CLK_AUDSYS_22M 1
|
||
|
|
#define CLK_AUDSYS_24M 2
|
||
|
|
#define CLK_AUDSYS_APLL2_TUNER 3
|
||
|
|
#define CLK_AUDSYS_APLL_TUNER 4
|
||
|
|
#define CLK_AUDSYS_TDM 5
|
||
|
|
#define CLK_AUDSYS_ADC 6
|
||
|
|
#define CLK_AUDSYS_DAC 7
|
||
|
|
#define CLK_AUDSYS_DAC_PREDIS 8
|
||
|
|
#define CLK_AUDSYS_TML 9
|
||
|
|
#define CLK_AUDSYS_NLE 10
|
||
|
|
#define CLK_AUDSYS_I2S1_BCLK 11
|
||
|
|
#define CLK_AUDSYS_I2S2_BCLK 12
|
||
|
|
#define CLK_AUDSYS_I2S3_BCLK 13
|
||
|
|
#define CLK_AUDSYS_I2S4_BCLK 14
|
||
|
|
#define CLK_AUDSYS_CONNSYS_I2S_ASRC 15
|
||
|
|
#define CLK_AUDSYS_GENERAL1_ASRC 16
|
||
|
|
#define CLK_AUDSYS_GENERAL2_ASRC 17
|
||
|
|
#define CLK_AUDSYS_DAC_HIRES 18
|
||
|
|
#define CLK_AUDSYS_ADC_HIRES 19
|
||
|
|
#define CLK_AUDSYS_ADC_HIRES_TML 20
|
||
|
|
#define CLK_AUDSYS_ADDA6_ADC 21
|
||
|
|
#define CLK_AUDSYS_ADDA6_ADC_HIRES 22
|
||
|
|
#define CLK_AUDSYS_3RD_DAC 23
|
||
|
|
#define CLK_AUDSYS_3RD_DAC_PREDIS 24
|
||
|
|
#define CLK_AUDSYS_3RD_DAC_TML 25
|
||
|
|
#define CLK_AUDSYS_3RD_DAC_HIRES 26
|
||
|
|
#define CLK_AUDSYS_I2S5_BCLK 27
|
||
|
|
#define CLK_AUDSYS_I2S6_BCLK 28
|
||
|
|
#define CLK_AUDSYS_I2S7_BCLK 29
|
||
|
|
#define CLK_AUDSYS_I2S8_BCLK 30
|
||
|
|
#define CLK_AUDSYS_I2S9_BCLK 31
|
||
|
|
#define CLK_AUDSYS_NR_CLK 32
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_E */
|
||
|
|
|
||
|
|
#define CLK_IMPE_AP_CLOCK_RO_I2C3 0
|
||
|
|
#define CLK_IMPE_NR_CLK 1
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_S */
|
||
|
|
|
||
|
|
#define CLK_IMPS_AP_CLOCK_RO_I2C5 0
|
||
|
|
#define CLK_IMPS_AP_CLOCK_RO_I2C7 1
|
||
|
|
#define CLK_IMPS_AP_CLOCK_RO_I2C8 2
|
||
|
|
#define CLK_IMPS_AP_CLOCK_RO_I2C9 3
|
||
|
|
#define CLK_IMPS_NR_CLK 4
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_WS */
|
||
|
|
|
||
|
|
#define CLK_IMPWS_AP_CLOCK_RO_I2C1 0
|
||
|
|
#define CLK_IMPWS_AP_CLOCK_RO_I2C2 1
|
||
|
|
#define CLK_IMPWS_AP_CLOCK_RO_I2C4 2
|
||
|
|
#define CLK_IMPWS_NR_CLK 3
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_W */
|
||
|
|
|
||
|
|
#define CLK_IMPW_AP_CLOCK_RO_I2C0 0
|
||
|
|
#define CLK_IMPW_NR_CLK 1
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_N */
|
||
|
|
|
||
|
|
#define CLK_IMPN_AP_CLOCK_RO_I2C6 0
|
||
|
|
#define CLK_IMPN_NR_CLK 1
|
||
|
|
|
||
|
|
/* MFGSYS */
|
||
|
|
|
||
|
|
#define CLK_MFGCFG_BG3D 0
|
||
|
|
#define CLK_MFGCFG_NR_CLK 1
|
||
|
|
|
||
|
|
/* MMSYS_CONFIG */
|
||
|
|
|
||
|
|
#define CLK_MM_DISP_MUTEX0 0
|
||
|
|
#define CLK_MM_APB_BUS 1
|
||
|
|
#define CLK_MM_DISP_OVL0 2
|
||
|
|
#define CLK_MM_DISP_RDMA0 3
|
||
|
|
#define CLK_MM_DISP_OVL0_2L 4
|
||
|
|
#define CLK_MM_DISP_WDMA0 5
|
||
|
|
#define CLK_MM_DISP_CCORR1 6
|
||
|
|
#define CLK_MM_DISP_RSZ0 7
|
||
|
|
#define CLK_MM_DISP_AAL0 8
|
||
|
|
#define CLK_MM_DISP_CCORR0 9
|
||
|
|
#define CLK_MM_DISP_COLOR0 10
|
||
|
|
#define CLK_MM_SMI_INFRA 11
|
||
|
|
#define CLK_MM_DISP_DSC_WRAP 12
|
||
|
|
#define CLK_MM_DISP_GAMMA0 13
|
||
|
|
#define CLK_MM_DISP_POSTMASK0 14
|
||
|
|
#define CLK_MM_DISP_SPR0 15
|
||
|
|
#define CLK_MM_DISP_DITHER0 16
|
||
|
|
#define CLK_MM_SMI_COMMON 17
|
||
|
|
#define CLK_MM_DISP_CM0 18
|
||
|
|
#define CLK_MM_DSI0 19
|
||
|
|
#define CLK_MM_DISP_FAKE_ENG0 20
|
||
|
|
#define CLK_MM_DISP_FAKE_ENG1 21
|
||
|
|
#define CLK_MM_SMI_GALS 22
|
||
|
|
#define CLK_MM_SMI_IOMMU 23
|
||
|
|
#define CLK_MM_DSI0_DSI_CK_DOMAIN 24
|
||
|
|
#define CLK_MM_DISP_26M 25
|
||
|
|
#define CLK_MM_NR_CLK 26
|
||
|
|
|
||
|
|
/* IMGSYS1 */
|
||
|
|
|
||
|
|
#define CLK_IMGSYS1_LARB9 0
|
||
|
|
#define CLK_IMGSYS1_LARB10 1
|
||
|
|
#define CLK_IMGSYS1_DIP 2
|
||
|
|
#define CLK_IMGSYS1_GALS 3
|
||
|
|
#define CLK_IMGSYS1_NR_CLK 4
|
||
|
|
|
||
|
|
/* IMGSYS2 */
|
||
|
|
|
||
|
|
#define CLK_IMGSYS2_LARB9 0
|
||
|
|
#define CLK_IMGSYS2_LARB10 1
|
||
|
|
#define CLK_IMGSYS2_MFB 2
|
||
|
|
#define CLK_IMGSYS2_WPE 3
|
||
|
|
#define CLK_IMGSYS2_MSS 4
|
||
|
|
#define CLK_IMGSYS2_GALS 5
|
||
|
|
#define CLK_IMGSYS2_NR_CLK 6
|
||
|
|
|
||
|
|
/* VDEC_GCON */
|
||
|
|
|
||
|
|
#define CLK_VDEC_LARB1_CKEN 0
|
||
|
|
#define CLK_VDEC_CKEN 1
|
||
|
|
#define CLK_VDEC_ACTIVE 2
|
||
|
|
#define CLK_VDEC_NR_CLK 3
|
||
|
|
|
||
|
|
/* VENC_GCON */
|
||
|
|
|
||
|
|
#define CLK_VENC_SET0_LARB 0
|
||
|
|
#define CLK_VENC_SET1_VENC 1
|
||
|
|
#define CLK_VENC_SET2_JPGENC 2
|
||
|
|
#define CLK_VENC_SET5_GALS 3
|
||
|
|
#define CLK_VENC_NR_CLK 4
|
||
|
|
|
||
|
|
/* APU_CONN */
|
||
|
|
|
||
|
|
#define CLK_APUC_APU 0
|
||
|
|
#define CLK_APUC_AHB 1
|
||
|
|
#define CLK_APUC_AXI 2
|
||
|
|
#define CLK_APUC_ISP 3
|
||
|
|
#define CLK_APUC_CAM_ADL 4
|
||
|
|
#define CLK_APUC_IMG_ADL 5
|
||
|
|
#define CLK_APUC_EMI_26M 6
|
||
|
|
#define CLK_APUC_VPU_UDI 7
|
||
|
|
#define CLK_APUC_EDMA_0 8
|
||
|
|
#define CLK_APUC_EDMA_1 9
|
||
|
|
#define CLK_APUC_EDMAL_0 10
|
||
|
|
#define CLK_APUC_EDMAL_1 11
|
||
|
|
#define CLK_APUC_MNOC 12
|
||
|
|
#define CLK_APUC_TCM 13
|
||
|
|
#define CLK_APUC_MD32 14
|
||
|
|
#define CLK_APUC_IOMMU_0 15
|
||
|
|
#define CLK_APUC_MD32_32K 16
|
||
|
|
#define CLK_APUC_NR_CLK 17
|
||
|
|
|
||
|
|
/* APU_VCORE */
|
||
|
|
|
||
|
|
#define CLK_APUV_AHB 0
|
||
|
|
#define CLK_APUV_AXI 1
|
||
|
|
#define CLK_APUV_ADL 2
|
||
|
|
#define CLK_APUV_QOS 3
|
||
|
|
#define CLK_APUV_NR_CLK 4
|
||
|
|
|
||
|
|
/* APU0 */
|
||
|
|
|
||
|
|
#define CLK_APU0_APU 0
|
||
|
|
#define CLK_APU0_AXI_M 1
|
||
|
|
#define CLK_APU0_JTAG 2
|
||
|
|
#define CLK_APU0_PCLK 3
|
||
|
|
#define CLK_APU0_NR_CLK 4
|
||
|
|
|
||
|
|
/* APU1 */
|
||
|
|
|
||
|
|
#define CLK_APU1_APU 0
|
||
|
|
#define CLK_APU1_AXI_M 1
|
||
|
|
#define CLK_APU1_JTAG 2
|
||
|
|
#define CLK_APU1_PCLK 3
|
||
|
|
#define CLK_APU1_NR_CLK 4
|
||
|
|
|
||
|
|
/* CAMSYS_MAIN */
|
||
|
|
|
||
|
|
#define CLK_CAM_M_LARB13 0
|
||
|
|
#define CLK_CAM_M_LARB14 1
|
||
|
|
#define CLK_CAM_M_RESERVED0 2
|
||
|
|
#define CLK_CAM_M_CAM 3
|
||
|
|
#define CLK_CAM_M_CAMTG 4
|
||
|
|
#define CLK_CAM_M_SENINF 5
|
||
|
|
#define CLK_CAM_M_CAMSV1 6
|
||
|
|
#define CLK_CAM_M_CAMSV2 7
|
||
|
|
#define CLK_CAM_M_CAMSV3 8
|
||
|
|
#define CLK_CAM_M_CCU0 9
|
||
|
|
#define CLK_CAM_M_CCU1 10
|
||
|
|
#define CLK_CAM_M_MRAW0 11
|
||
|
|
#define CLK_CAM_M_RESERVED2 12
|
||
|
|
#define CLK_CAM_M_FAKE_ENG 13
|
||
|
|
#define CLK_CAM_M_CCU_GALS 14
|
||
|
|
#define CLK_CAM_M_CAM2MM_GALS 15
|
||
|
|
#define CLK_CAM_M_NR_CLK 16
|
||
|
|
|
||
|
|
/* CAMSYS_RAWA */
|
||
|
|
|
||
|
|
#define CLK_CAM_RA_LARBX 0
|
||
|
|
#define CLK_CAM_RA_CAM 1
|
||
|
|
#define CLK_CAM_RA_CAMTG 2
|
||
|
|
#define CLK_CAM_RA_NR_CLK 3
|
||
|
|
|
||
|
|
/* CAMSYS_RAWB */
|
||
|
|
|
||
|
|
#define CLK_CAM_RB_LARBX 0
|
||
|
|
#define CLK_CAM_RB_CAM 1
|
||
|
|
#define CLK_CAM_RB_CAMTG 2
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#define CLK_CAM_RB_NR_CLK 3
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||
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/* IPESYS */
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#define CLK_IPE_LARB19 0
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#define CLK_IPE_LARB20 1
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#define CLK_IPE_SMI_SUBCOM 2
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#define CLK_IPE_FD 3
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#define CLK_IPE_FE 4
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#define CLK_IPE_RSC 5
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#define CLK_IPE_DPE 6
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#define CLK_IPE_GALS 7
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#define CLK_IPE_NR_CLK 8
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||
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/* MDPSYS_CONFIG */
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#define CLK_MDP_RDMA0 0
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#define CLK_MDP_TDSHP0 1
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#define CLK_MDP_IMG_DL_ASYNC0 2
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#define CLK_MDP_IMG_DL_ASYNC1 3
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#define CLK_MDP_RDMA1 4
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||
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#define CLK_MDP_TDSHP1 5
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||
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#define CLK_MDP_SMI0 6
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||
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#define CLK_MDP_APB_BUS 7
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||
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#define CLK_MDP_WROT0 8
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||
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#define CLK_MDP_RSZ0 9
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||
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#define CLK_MDP_HDR0 10
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||
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#define CLK_MDP_MUTEX0 11
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||
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#define CLK_MDP_WROT1 12
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||
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#define CLK_MDP_RSZ1 13
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||
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#define CLK_MDP_FAKE_ENG0 14
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||
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#define CLK_MDP_AAL0 15
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||
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#define CLK_MDP_AAL1 16
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||
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#define CLK_MDP_COLOR0 17
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||
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|
#define CLK_MDP_IMG_DL_RELAY0_ASYNC0 18
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||
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|
#define CLK_MDP_IMG_DL_RELAY1_ASYNC1 19
|
||
|
|
#define CLK_MDP_NR_CLK 20
|
||
|
|
|
||
|
|
/* SCP_SYS */
|
||
|
|
#define SCP_SYS_MD1 0
|
||
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|
#define SCP_SYS_CONN 1
|
||
|
|
#define SCP_SYS_MFG0 2
|
||
|
|
#define SCP_SYS_MFG1 3
|
||
|
|
#define SCP_SYS_MFG2 4
|
||
|
|
#define SCP_SYS_MFG3 5
|
||
|
|
#define SCP_SYS_MFG5 6
|
||
|
|
#define SCP_SYS_ISP 7
|
||
|
|
#define SCP_SYS_ISP2 8
|
||
|
|
#define SCP_SYS_IPE 9
|
||
|
|
#define SCP_SYS_VDEC 10
|
||
|
|
#define SCP_SYS_VENC 11
|
||
|
|
#define SCP_SYS_DIS 12
|
||
|
|
#define SCP_SYS_AUDIO 13
|
||
|
|
#define SCP_SYS_ADSP 14
|
||
|
|
#define SCP_SYS_CAM 15
|
||
|
|
#define SCP_SYS_CAM_RAWA 16
|
||
|
|
#define SCP_SYS_CAM_RAWB 17
|
||
|
|
#define SCP_SYS_VPU 18
|
||
|
|
#define SCP_NR_SYSS 19
|
||
|
|
|
||
|
|
#endif /* _DT_BINDINGS_CLK_MT6853_H */
|
||
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