795 lines
22 KiB
C
795 lines
22 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT6893_H
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#define _DT_BINDINGS_CLK_MT6893_H
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/* TOPCKGEN */
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#define CLK_TOP_ARMPLL_BL0_CK_VRPOC 0
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#define CLK_TOP_ARMPLL_BL1_CK_VRPOC 1
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#define CLK_TOP_ARMPLL_BL2_CK_VRPOC 2
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#define CLK_TOP_ARMPLL_BL3_CK_VRPOC 3
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#define CLK_TOP_ARMPLL_LL_CK_VRPOC 4
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#define CLK_TOP_CCIPLL_CK_VRPOC_CCI 5
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#define CLK_TOP_MFGPLL 6
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#define CLK_TOP_MAINPLL 7
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#define CLK_TOP_MAINPLL_D3 8
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#define CLK_TOP_MAINPLL_D4 9
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#define CLK_TOP_MAINPLL_D4_D2 10
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#define CLK_TOP_MAINPLL_D4_D4 11
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#define CLK_TOP_MAINPLL_D4_D8 12
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#define CLK_TOP_MAINPLL_D4_D16 13
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#define CLK_TOP_MAINPLL_D5 14
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#define CLK_TOP_MAINPLL_D5_D2 15
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#define CLK_TOP_MAINPLL_D5_D4 16
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#define CLK_TOP_MAINPLL_D5_D8 17
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#define CLK_TOP_MAINPLL_D6 18
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#define CLK_TOP_MAINPLL_D6_D2 19
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#define CLK_TOP_MAINPLL_D6_D4 20
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#define CLK_TOP_MAINPLL_D6_D8 21
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#define CLK_TOP_MAINPLL_D7 22
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#define CLK_TOP_MAINPLL_D7_D2 23
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#define CLK_TOP_MAINPLL_D7_D4 24
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#define CLK_TOP_MAINPLL_D7_D8 25
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#define CLK_TOP_MAINPLL_D9 26
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#define CLK_TOP_UNIVPLL 27
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#define CLK_TOP_UNIVPLL_D2 28
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#define CLK_TOP_UNIVPLL_D3 29
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#define CLK_TOP_UNIVPLL_D4 30
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#define CLK_TOP_UNIVPLL_D4_D2 31
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#define CLK_TOP_UNIVPLL_D4_D4 32
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#define CLK_TOP_UNIVPLL_D4_D8 33
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#define CLK_TOP_UNIVPLL_D5 34
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#define CLK_TOP_UNIVPLL_D5_D2 35
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#define CLK_TOP_UNIVPLL_D5_D4 36
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#define CLK_TOP_UNIVPLL_D5_D8 37
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#define CLK_TOP_UNIVPLL_D5_D16 38
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#define CLK_TOP_UNIVPLL_D6 39
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#define CLK_TOP_UNIVPLL_D6_D2 40
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#define CLK_TOP_UNIVPLL_D6_D4 41
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#define CLK_TOP_UNIVPLL_D6_D8 42
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#define CLK_TOP_UNIVPLL_D6_D16 43
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#define CLK_TOP_UNIVPLL_D7 44
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#define CLK_TOP_UNIVPLL_D7_D2 45
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#define CLK_TOP_UNIVPLL_192M_D2 46
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#define CLK_TOP_UNIVPLL_192M_D4 47
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#define CLK_TOP_UNIVPLL_192M_D8 48
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#define CLK_TOP_UNIVPLL_192M_D16 49
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#define CLK_TOP_UNIVPLL_192M_D32 50
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#define CLK_TOP_USB20_192M 51
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#define CLK_TOP_USB20_PLL_D2 52
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#define CLK_TOP_USB20_PLL_D4 53
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#define CLK_TOP_MPLL_208M 54
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#define CLK_TOP_MPLL_D2 55
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#define CLK_TOP_MPLL_D4 56
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#define CLK_TOP_APLL1 57
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#define CLK_TOP_APLL1_D2 58
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#define CLK_TOP_APLL1_D4 59
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#define CLK_TOP_APLL1_D8 60
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#define CLK_TOP_APLL2 61
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#define CLK_TOP_APLL2_D2 62
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#define CLK_TOP_APLL2_D4 63
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#define CLK_TOP_APLL2_D8 64
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#define CLK_TOP_CLK26M_BYP 65
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#define CLK_TOP_ADSPPLL 66
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#define CLK_TOP_ADSPPLL_D4 67
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#define CLK_TOP_ADSPPLL_D5 68
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#define CLK_TOP_ADSPPLL_D6 69
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#define CLK_TOP_MMPLL 70
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#define CLK_TOP_MMPLL_D3 71
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#define CLK_TOP_MMPLL_D4 72
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#define CLK_TOP_MMPLL_D4_D2 73
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#define CLK_TOP_MMPLL_D4_D4 74
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#define CLK_TOP_MMPLL_D5 75
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#define CLK_TOP_MMPLL_D5_D2 76
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#define CLK_TOP_MMPLL_D5_D4 77
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#define CLK_TOP_MMPLL_D6 78
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#define CLK_TOP_MMPLL_D6_D2 79
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#define CLK_TOP_MMPLL_D7 80
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#define CLK_TOP_MMPLL_D9 81
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#define CLK_TOP_APUPLL 82
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#define CLK_TOP_TVDPLL 83
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#define CLK_TOP_TVDPLL_D2 84
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#define CLK_TOP_TVDPLL_D4 85
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#define CLK_TOP_TVDPLL_D8 86
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#define CLK_TOP_TVDPLL_D16 87
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#define CLK_TOP_MSDCPLL 88
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#define CLK_TOP_MSDCPLL_D2 89
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#define CLK_TOP_MSDCPLL_D4 90
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#define CLK_TOP_MSDCPLL_D8 91
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#define CLK_TOP_MSDCPLL_D16 92
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#define CLK_TOP_MIPI_26M 93
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#define CLK_TOP_MEM_26M 94
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#define CLK_TOP_ARMPLL_26M 95
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#define CLK_TOP_SSUBS_26M 96
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#define CLK_TOP_PLLGP_TST 97
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#define CLK_TOP_CLKRTC 98
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#define CLK_TOP_TCK_26M_MX8 99
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#define CLK_TOP_TCK_26M_MX9 100
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#define CLK_TOP_TCK_26M_MX10 101
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#define CLK_TOP_TCK_26M_MX11 102
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#define CLK_TOP_TCK_26M_MX12 103
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#define CLK_TOP_CSW_FAXI 104
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#define CLK_TOP_F26M_CK_D52 105
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#define CLK_TOP_F26M_CK_D2 106
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#define CLK_TOP_OSC 107
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#define CLK_TOP_OSC_D2 108
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#define CLK_TOP_OSC_D4 109
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#define CLK_TOP_OSC_D8 110
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#define CLK_TOP_OSC_D16 111
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#define CLK_TOP_OSC_D10 112
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#define CLK_TOP_OSC_D20 113
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#define CLK_TOP_TVDPLL_MAINPLL_D2 114
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#define CLK_TOP_F26M 115
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#define CLK_TOP_FRTC 116
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#define CLK_TOP_AXI 117
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#define CLK_TOP_SPM 118
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#define CLK_TOP_SCP 119
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#define CLK_TOP_BUS 120
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#define CLK_TOP_DISP 121
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#define CLK_TOP_MDP 122
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#define CLK_TOP_IMG1 123
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#define CLK_TOP_IMG2 124
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#define CLK_TOP_IPE 125
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#define CLK_TOP_DPE 126
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#define CLK_TOP_CAM 127
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#define CLK_TOP_CCU 128
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#define CLK_TOP_DSP 129
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#define CLK_TOP_DSP1 130
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#define CLK_TOP_DSP2 131
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#define CLK_TOP_DSP3 132
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#define CLK_TOP_DSP4 133
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#define CLK_TOP_DSP5 134
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#define CLK_TOP_DSP6 135
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#define CLK_TOP_DSP7 136
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#define CLK_TOP_IPU_IF 137
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#define CLK_TOP_MFG_REF 138
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#define CLK_TOP_FCAMTG 139
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#define CLK_TOP_FCAMTG2 140
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#define CLK_TOP_FCAMTG3 141
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#define CLK_TOP_FCAMTG4 142
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#define CLK_TOP_FUART 143
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#define CLK_TOP_SPI 144
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#define CLK_TOP_MSDC50_0_HCLK 145
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#define CLK_TOP_MSDC50_0 146
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#define CLK_TOP_MSDC30_1 147
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#define CLK_TOP_AUDIO 148
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#define CLK_TOP_AUD_INTBUS 149
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#define CLK_TOP_FPWRAP_ULPOSC 150
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#define CLK_TOP_ATB 151
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#define CLK_TOP_SSPM 152
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#define CLK_TOP_DP 153
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#define CLK_TOP_SCAM 154
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#define CLK_TOP_FDISP_PWM 155
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#define CLK_TOP_FUSB_TOP 156
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#define CLK_TOP_FSSUSB_XHCI 157
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#define CLK_TOP_I2C 158
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#define CLK_TOP_FSENINF 159
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#define CLK_TOP_FSENINF1 160
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#define CLK_TOP_FSENINF2 161
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#define CLK_TOP_FSENINF3 162
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#define CLK_TOP_DXCC 163
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#define CLK_TOP_AUD_ENGEN1 164
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#define CLK_TOP_AUD_ENGEN2 165
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#define CLK_TOP_AES_UFSFDE 166
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#define CLK_TOP_UFS 167
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#define CLK_TOP_AUD_1 168
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#define CLK_TOP_AUD_2 169
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#define CLK_TOP_ADSP 170
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#define CLK_TOP_DPMAIF_MAIN 171
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#define CLK_TOP_VENC 172
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#define CLK_TOP_VDEC 173
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#define CLK_TOP_VDEC_LAT 174
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#define CLK_TOP_CAMTM 175
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#define CLK_TOP_PWM 176
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#define CLK_TOP_AUDIO_H 177
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#define CLK_TOP_FCAMTG5 178
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#define CLK_TOP_FCAMTG6 179
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#define CLK_TOP_MCUPM 180
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#define CLK_TOP_SPMI_MST 181
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#define CLK_TOP_DVFSRC 182
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#define CLK_TOP_SRCK 183
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#define CLK_TOP_SYS_26M 184
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#define CLK_TOP_F_UFS_MP_SAP_CFG 185
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#define CLK_TOP_F_UFS_TICK1US 186
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#define CLK_TOP_I2C_PSEUDO 187
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#define CLK_TOP_APDMA_PSEUDO 188
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#define CLK_TOP_AXI_SEL 189
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#define CLK_TOP_SPM_SEL 190
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#define CLK_TOP_SCP_SEL 191
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#define CLK_TOP_BUS_AXIMEM_SEL 192
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#define CLK_TOP_DISP_SEL 193
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#define CLK_TOP_MDP_SEL 194
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#define CLK_TOP_IMG1_SEL 195
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#define CLK_TOP_IMG2_SEL 196
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#define CLK_TOP_IPE_SEL 197
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#define CLK_TOP_DPE_SEL 198
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#define CLK_TOP_CAM_SEL 199
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#define CLK_TOP_CCU_SEL 200
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#define CLK_TOP_DSP_SEL 201
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#define CLK_TOP_DSP1_SEL 202
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#define CLK_TOP_DSP2_SEL 203
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#define CLK_TOP_DSP3_SEL 204
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#define CLK_TOP_DSP4_SEL 205
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#define CLK_TOP_DSP5_SEL 206
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#define CLK_TOP_DSP6_SEL 207
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#define CLK_TOP_DSP7_SEL 208
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#define CLK_TOP_IPU_IF_SEL 209
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#define CLK_TOP_MFG_SEL 210
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#define CLK_TOP_CAMTG_SEL 211
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#define CLK_TOP_CAMTG2_SEL 212
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#define CLK_TOP_CAMTG3_SEL 213
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#define CLK_TOP_CAMTG4_SEL 214
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#define CLK_TOP_UART_SEL 215
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#define CLK_TOP_SPI_SEL 216
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#define CLK_TOP_MSDC50_0_HCLK_SEL 217
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#define CLK_TOP_MSDC50_0_SEL 218
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#define CLK_TOP_MSDC30_1_SEL 219
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#define CLK_TOP_AUDIO_SEL 220
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#define CLK_TOP_AUD_INTBUS_SEL 221
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#define CLK_TOP_PWRAP_ULPOSC_SEL 222
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#define CLK_TOP_ATB_SEL 223
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#define CLK_TOP_SSPM_SEL 224
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#define CLK_TOP_DP_SEL 225
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#define CLK_TOP_SCAM_SEL 226
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#define CLK_TOP_DISP_PWM_SEL 227
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#define CLK_TOP_USB_TOP_SEL 228
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#define CLK_TOP_SSUSB_XHCI_SEL 229
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#define CLK_TOP_I2C_SEL 230
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#define CLK_TOP_SENINF_SEL 231
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#define CLK_TOP_SENINF1_SEL 232
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#define CLK_TOP_SENINF2_SEL 233
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#define CLK_TOP_SENINF3_SEL 234
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#define CLK_TOP_DXCC_SEL 235
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#define CLK_TOP_AUD_ENGEN1_SEL 236
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#define CLK_TOP_AUD_ENGEN2_SEL 237
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#define CLK_TOP_AES_UFSFDE_SEL 238
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#define CLK_TOP_UFS_SEL 239
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#define CLK_TOP_AUD_1_SEL 240
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#define CLK_TOP_AUD_2_SEL 241
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#define CLK_TOP_ADSP_SEL 242
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#define CLK_TOP_DPMAIF_MAIN_SEL 243
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#define CLK_TOP_VENC_SEL 244
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#define CLK_TOP_VDEC_SEL 245
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#define CLK_TOP_VDEC_LAT_SEL 246
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#define CLK_TOP_CAMTM_SEL 247
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#define CLK_TOP_PWM_SEL 248
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#define CLK_TOP_AUDIO_H_SEL 249
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#define CLK_TOP_CAMTG5_SEL 250
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#define CLK_TOP_CAMTG6_SEL 251
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#define CLK_TOP_MCUPM_SEL 252
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#define CLK_TOP_SPMI_MST_SEL 253
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#define CLK_TOP_DVFSRC_SEL 254
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#define CLK_TOP_APLL_I2S0_MCK_SEL 255
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#define CLK_TOP_APLL_I2S1_MCK_SEL 256
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#define CLK_TOP_APLL_I2S2_MCK_SEL 257
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#define CLK_TOP_APLL_I2S3_MCK_SEL 258
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#define CLK_TOP_APLL_I2S4_MCK_SEL 259
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#define CLK_TOP_APLL_I2S5_MCK_SEL 260
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#define CLK_TOP_APLL_I2S6_MCK_SEL 261
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#define CLK_TOP_APLL_I2S7_MCK_SEL 262
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#define CLK_TOP_APLL_I2S8_MCK_SEL 263
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#define CLK_TOP_APLL_I2S9_MCK_SEL 264
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#define CLK_TOP_APLL1_CK_DIV0 265
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#define CLK_TOP_APLL2_CK_DIV0 266
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#define CLK_TOP_APLL12_CK_DIV0 267
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#define CLK_TOP_APLL12_CK_DIV1 268
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#define CLK_TOP_APLL12_CK_DIV2 269
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#define CLK_TOP_APLL12_CK_DIV3 270
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#define CLK_TOP_APLL12_CK_DIV4 271
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#define CLK_TOP_APLL12_CK_DIVB 272
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#define CLK_TOP_APLL12_CK_DIV5_LSB 273
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#define CLK_TOP_APLL12_CK_DIV5_MSB 274
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#define CLK_TOP_APLL12_CK_DIV6 275
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#define CLK_TOP_APLL12_CK_DIV7 276
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#define CLK_TOP_APLL12_CK_DIV8 277
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#define CLK_TOP_APLL12_CK_DIV9 278
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#define CLK_TOP_NR_CLK 279
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/* INFRACFG_AO */
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#define CLK_IFRAO_PMIC_TMR 0
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#define CLK_IFRAO_PMIC_AP 1
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#define CLK_IFRAO_GCE 2
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#define CLK_IFRAO_GCE2 3
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#define CLK_IFRAO_THERM 4
|
||
|
|
#define CLK_IFRAO_I2C0 5
|
||
|
|
#define CLK_IFRAO_I2C1 6
|
||
|
|
#define CLK_IFRAO_I2C2 7
|
||
|
|
#define CLK_IFRAO_I2C3 8
|
||
|
|
#define CLK_IFRAO_PWM_HCLK 9
|
||
|
|
#define CLK_IFRAO_PWM1 10
|
||
|
|
#define CLK_IFRAO_PWM2 11
|
||
|
|
#define CLK_IFRAO_PWM3 12
|
||
|
|
#define CLK_IFRAO_PWM4 13
|
||
|
|
#define CLK_IFRAO_PWM 14
|
||
|
|
#define CLK_IFRAO_UART0 15
|
||
|
|
#define CLK_IFRAO_UART1 16
|
||
|
|
#define CLK_IFRAO_UART2 17
|
||
|
|
#define CLK_IFRAO_UART3 18
|
||
|
|
#define CLK_IFRAO_GCE_26M 19
|
||
|
|
#define CLK_IFRAO_CQ_DMA_FPC 20
|
||
|
|
#define CLK_IFRAO_BTIF 21
|
||
|
|
#define CLK_IFRAO_SPI0 22
|
||
|
|
#define CLK_IFRAO_MSDC0 23
|
||
|
|
#define CLK_IFRAO_MSDC1 24
|
||
|
|
#define CLK_IFRAO_MSDC0_SRC 25
|
||
|
|
#define CLK_IFRAO_AUXADC 26
|
||
|
|
#define CLK_IFRAO_CPUM 27
|
||
|
|
#define CLK_IFRAO_CCIF1_AP 28
|
||
|
|
#define CLK_IFRAO_CCIF1_MD 29
|
||
|
|
#define CLK_IFRAO_MSDC1_SRC 30
|
||
|
|
#define CLK_IFRAO_AP_DMA_PS 31
|
||
|
|
#define CLK_IFRAO_DEVICE_APC 32
|
||
|
|
#define CLK_IFRAO_CCIF_AP 33
|
||
|
|
#define CLK_IFRAO_AUDIO 34
|
||
|
|
#define CLK_IFRAO_CCIF_MD 35
|
||
|
|
#define CLK_IFRAO_DXCC_SEC_CORE 36
|
||
|
|
#define CLK_IFRAO_SSUSB 37
|
||
|
|
#define CLK_IFRAO_DISP_PWM 38
|
||
|
|
#define CLK_IFRAO_DPMAIF 39
|
||
|
|
#define CLK_IFRAO_AUDIO_26M_BCLK 40
|
||
|
|
#define CLK_IFRAO_SPI1 41
|
||
|
|
#define CLK_IFRAO_I2C4 42
|
||
|
|
#define CLK_IFRAO_SPI2 43
|
||
|
|
#define CLK_IFRAO_SPI3 44
|
||
|
|
#define CLK_IFRAO_UNIPRO_SYSCLK 45
|
||
|
|
#define CLK_IFRAO_UFS_MP_SAP_BCLK 46
|
||
|
|
#define CLK_IFRAO_I2C5 47
|
||
|
|
#define CLK_IFRAO_I2C5_ARBITER 48
|
||
|
|
#define CLK_IFRAO_I2C5_IMM 49
|
||
|
|
#define CLK_IFRAO_I2C1_ARBITER 50
|
||
|
|
#define CLK_IFRAO_I2C1_IMM 51
|
||
|
|
#define CLK_IFRAO_I2C2_ARBITER 52
|
||
|
|
#define CLK_IFRAO_I2C2_IMM 53
|
||
|
|
#define CLK_IFRAO_SPI4 54
|
||
|
|
#define CLK_IFRAO_SPI5 55
|
||
|
|
#define CLK_IFRAO_CQ_DMA 56
|
||
|
|
#define CLK_IFRAO_UFS 57
|
||
|
|
#define CLK_IFRAO_AES 58
|
||
|
|
#define CLK_IFRAO_SSUSB_XHCI 59
|
||
|
|
#define CLK_IFRAO_MSDC0_SELF 60
|
||
|
|
#define CLK_IFRAO_MSDC1_SELF 61
|
||
|
|
#define CLK_IFRAO_MSDC2_SELF 62
|
||
|
|
#define CLK_IFRAO_I2C6 63
|
||
|
|
#define CLK_IFRAO_AP_MSDC0 64
|
||
|
|
#define CLK_IFRAO_MD_MSDC0 65
|
||
|
|
#define CLK_IFRAO_CCIF5_AP 66
|
||
|
|
#define CLK_IFRAO_CCIF5_MD 67
|
||
|
|
#define CLK_IFRAO_CCIF2_AP 68
|
||
|
|
#define CLK_IFRAO_CCIF2_MD 69
|
||
|
|
#define CLK_IFRAO_I2C7 70
|
||
|
|
#define CLK_IFRAO_I2C8 71
|
||
|
|
#define CLK_IFRAO_FBIST2FPC 72
|
||
|
|
#define CLK_IFRAO_DEVICE_APC_SYNC 73
|
||
|
|
#define CLK_IFRAO_DPMAIF_MAIN 74
|
||
|
|
#define CLK_IFRAO_CCIF4_AP 75
|
||
|
|
#define CLK_IFRAO_CCIF4_MD 76
|
||
|
|
#define CLK_IFRAO_SPI6_CK 77
|
||
|
|
#define CLK_IFRAO_SPI7_CK 78
|
||
|
|
#define CLK_IFRAO_APDMA 79
|
||
|
|
#define CLK_IFRAO_NR_CLK 80
|
||
|
|
|
||
|
|
/* APMIXEDSYS */
|
||
|
|
#define CLK_APMIXED_ARMPLL_LL 0
|
||
|
|
#define CLK_APMIXED_ARMPLL_BL0 1
|
||
|
|
#define CLK_APMIXED_ARMPLL_BL1 2
|
||
|
|
#define CLK_APMIXED_ARMPLL_BL2 3
|
||
|
|
#define CLK_APMIXED_ARMPLL_BL3 4
|
||
|
|
#define CLK_APMIXED_CCIPLL 5
|
||
|
|
#define CLK_APMIXED_MAINPLL 6
|
||
|
|
#define CLK_APMIXED_UNIVPLL 7
|
||
|
|
#define CLK_APMIXED_MSDCPLL 8
|
||
|
|
#define CLK_APMIXED_MMPLL 9
|
||
|
|
#define CLK_APMIXED_ADSPPLL 10
|
||
|
|
#define CLK_APMIXED_MFGPLL 11
|
||
|
|
#define CLK_APMIXED_TVDPLL 12
|
||
|
|
#define CLK_APMIXED_APLL1 13
|
||
|
|
#define CLK_APMIXED_APLL2 14
|
||
|
|
#define CLK_APMIXED_MPLL 15
|
||
|
|
#define CLK_APMIXED_APUPLL 16
|
||
|
|
#define CLK_APMIXED_NR_CLK 17
|
||
|
|
|
||
|
|
/* SCP_ADSP */
|
||
|
|
#define CLK_SCP_ADSP_RG_AUDIODSP 0
|
||
|
|
#define CLK_SCP_ADSP_NR_CLK 1
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_C */
|
||
|
|
#define CLK_IMPC_AP_I2C0_RO 0
|
||
|
|
#define CLK_IMPC_AP_I2C10_RO 1
|
||
|
|
#define CLK_IMPC_AP_I2C11_RO 2
|
||
|
|
#define CLK_IMPC_AP_I2C12_RO 3
|
||
|
|
#define CLK_IMPC_AP_I2C13_RO 4
|
||
|
|
#define CLK_IMPC_NR_CLK 5
|
||
|
|
|
||
|
|
/* AUDIOSYS */
|
||
|
|
#define CLK_AUDSYS_AFE 0
|
||
|
|
#define CLK_AUDSYS_22M 1
|
||
|
|
#define CLK_AUDSYS_24M 2
|
||
|
|
#define CLK_AUDSYS_APLL2_TUNER 3
|
||
|
|
#define CLK_AUDSYS_APLL_TUNER 4
|
||
|
|
#define CLK_AUDSYS_TDM 5
|
||
|
|
#define CLK_AUDSYS_ADC 6
|
||
|
|
#define CLK_AUDSYS_DAC 7
|
||
|
|
#define CLK_AUDSYS_DAC_PREDIS 8
|
||
|
|
#define CLK_AUDSYS_TML 9
|
||
|
|
#define CLK_AUDSYS_NLE 10
|
||
|
|
#define CLK_AUDSYS_I2S1_BCLK 11
|
||
|
|
#define CLK_AUDSYS_I2S2_BCLK 12
|
||
|
|
#define CLK_AUDSYS_I2S3_BCLK 13
|
||
|
|
#define CLK_AUDSYS_I2S4_BCLK 14
|
||
|
|
#define CLK_AUDSYS_CONNSYS_I2S_ASRC 15
|
||
|
|
#define CLK_AUDSYS_GENERAL1_ASRC 16
|
||
|
|
#define CLK_AUDSYS_GENERAL2_ASRC 17
|
||
|
|
#define CLK_AUDSYS_DAC_HIRES 18
|
||
|
|
#define CLK_AUDSYS_ADC_HIRES 19
|
||
|
|
#define CLK_AUDSYS_ADC_HIRES_TML 20
|
||
|
|
#define CLK_AUDSYS_ADDA6_ADC 21
|
||
|
|
#define CLK_AUDSYS_ADDA6_ADC_HIRES 22
|
||
|
|
#define CLK_AUDSYS_3RD_DAC 23
|
||
|
|
#define CLK_AUDSYS_3RD_DAC_PREDIS 24
|
||
|
|
#define CLK_AUDSYS_3RD_DAC_TML 25
|
||
|
|
#define CLK_AUDSYS_3RD_DAC_HIRES 26
|
||
|
|
#define CLK_AUDSYS_I2S5_BCLK 27
|
||
|
|
#define CLK_AUDSYS_I2S6_BCLK 28
|
||
|
|
#define CLK_AUDSYS_I2S7_BCLK 29
|
||
|
|
#define CLK_AUDSYS_I2S8_BCLK 30
|
||
|
|
#define CLK_AUDSYS_I2S9_BCLK 31
|
||
|
|
#define CLK_AUDSYS_NR_CLK 32
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_E */
|
||
|
|
#define CLK_IMPE_AP_I2C3_RO 0
|
||
|
|
#define CLK_IMPE_AP_I2C9_RO 1
|
||
|
|
#define CLK_IMPE_NR_CLK 2
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_S */
|
||
|
|
#define CLK_IMPS_AP_I2C1_RO 0
|
||
|
|
#define CLK_IMPS_AP_I2C2_RO 1
|
||
|
|
#define CLK_IMPS_AP_I2C4_RO 2
|
||
|
|
#define CLK_IMPS_AP_I2C7_RO 3
|
||
|
|
#define CLK_IMPS_AP_I2C8_RO 4
|
||
|
|
#define CLK_IMPS_NR_CLK 5
|
||
|
|
|
||
|
|
/* IMP_IIC_WRAP_N */
|
||
|
|
#define CLK_IMPN_AP_I2C5_RO 0
|
||
|
|
#define CLK_IMPN_AP_I2C6_RO 1
|
||
|
|
#define CLK_IMPN_NR_CLK 2
|
||
|
|
|
||
|
|
/* MFGCFG */
|
||
|
|
#define CLK_MFGCFG_BG3D 0
|
||
|
|
#define CLK_MFGCFG_NR_CLK 1
|
||
|
|
|
||
|
|
/* MMSYS_CONFIG */
|
||
|
|
#define CLK_MM_DISP_RSZ0 0
|
||
|
|
#define CLK_MM_DISP_RSZ1 1
|
||
|
|
#define CLK_MM_DISP_OVL0 2
|
||
|
|
#define CLK_MM_INLINE 3
|
||
|
|
#define CLK_MM_MDP_TDSHP4 4
|
||
|
|
#define CLK_MM_MDP_TDSHP5 5
|
||
|
|
#define CLK_MM_MDP_AAL4 6
|
||
|
|
#define CLK_MM_MDP_AAL5 7
|
||
|
|
#define CLK_MM_MDP_HDR4 8
|
||
|
|
#define CLK_MM_MDP_HDR5 9
|
||
|
|
#define CLK_MM_MDP_RSZ4 10
|
||
|
|
#define CLK_MM_MDP_RSZ5 11
|
||
|
|
#define CLK_MM_MDP_RDMA4 12
|
||
|
|
#define CLK_MM_MDP_RDMA5 13
|
||
|
|
#define CLK_MM_DISP_FAKE_ENG0 14
|
||
|
|
#define CLK_MM_DISP_FAKE_ENG1 15
|
||
|
|
#define CLK_MM_DISP_OVL0_2L 16
|
||
|
|
#define CLK_MM_DISP_OVL1_2L 17
|
||
|
|
#define CLK_MM_DISP_OVL2_2L 18
|
||
|
|
#define CLK_MM_DISP_MUTEX 19
|
||
|
|
#define CLK_MM_DISP_OVL1 20
|
||
|
|
#define CLK_MM_DISP_OVL3_2L 21
|
||
|
|
#define CLK_MM_DISP_CCORR0 22
|
||
|
|
#define CLK_MM_DISP_CCORR1 23
|
||
|
|
#define CLK_MM_DISP_COLOR0 24
|
||
|
|
#define CLK_MM_DISP_COLOR1 25
|
||
|
|
#define CLK_MM_DISP_POSTMASK0 26
|
||
|
|
#define CLK_MM_DISP_POSTMASK1 27
|
||
|
|
#define CLK_MM_DISP_DITHER0 28
|
||
|
|
#define CLK_MM_DISP_DITHER1 29
|
||
|
|
#define CLK_MM_DSI0_MM_CLK 30
|
||
|
|
#define CLK_MM_DSI1_MM_CLK 31
|
||
|
|
#define CLK_MM_DISP_GAMMA0 32
|
||
|
|
#define CLK_MM_DISP_GAMMA1 33
|
||
|
|
#define CLK_MM_DISP_AAL0 34
|
||
|
|
#define CLK_MM_DISP_AAL1 35
|
||
|
|
#define CLK_MM_DISP_WDMA0 36
|
||
|
|
#define CLK_MM_DISP_WDMA1 37
|
||
|
|
#define CLK_MM_DISP_UFBC_WDMA0 38
|
||
|
|
#define CLK_MM_DISP_UFBC_WDMA1 39
|
||
|
|
#define CLK_MM_DISP_RDMA0 40
|
||
|
|
#define CLK_MM_DISP_RDMA1 41
|
||
|
|
#define CLK_MM_DISP_RDMA4 42
|
||
|
|
#define CLK_MM_DISP_RDMA5 43
|
||
|
|
#define CLK_MM_DISP_DSC_WRAP 44
|
||
|
|
#define CLK_MM_DP_INTF_MM_CLK 45
|
||
|
|
#define CLK_MM_DISP_MERGE0 46
|
||
|
|
#define CLK_MM_DISP_MERGE1 47
|
||
|
|
#define CLK_MM_SMI_COMMON 48
|
||
|
|
#define CLK_MM_SMI_GALS 49
|
||
|
|
#define CLK_MM_SMI_INFRA 50
|
||
|
|
#define CLK_MM_SMI_IOMMU 51
|
||
|
|
#define CLK_MM_DSI0_INTF_CLK 52
|
||
|
|
#define CLK_MM_DSI1_INTF_CLK 53
|
||
|
|
#define CLK_MM_DP_INTF_INTF_CLK 54
|
||
|
|
#define CLK_MM_CK_26_MHZ 55
|
||
|
|
#define CLK_MM_CK_32_KHZ 56
|
||
|
|
#define CLK_MM_NR_CLK 57
|
||
|
|
|
||
|
|
/* IMGSYS1 */
|
||
|
|
#define CLK_IMGSYS1_LARB9 0
|
||
|
|
#define CLK_IMGSYS1_LARB10 1
|
||
|
|
#define CLK_IMGSYS1_DIP 2
|
||
|
|
#define CLK_IMGSYS1_MFB 3
|
||
|
|
#define CLK_IMGSYS1_WPE 4
|
||
|
|
#define CLK_IMGSYS1_MSS 5
|
||
|
|
#define CLK_IMGSYS1_NR_CLK 6
|
||
|
|
|
||
|
|
/* IMGSYS2 */
|
||
|
|
#define CLK_IMGSYS2_LARB11 0
|
||
|
|
#define CLK_IMGSYS2_LARB12 1
|
||
|
|
#define CLK_IMGSYS2_DIP 2
|
||
|
|
#define CLK_IMGSYS2_WPE 3
|
||
|
|
#define CLK_IMGSYS2_NR_CLK 4
|
||
|
|
|
||
|
|
/* VDEC_SOC_GCON */
|
||
|
|
#define CLK_VDE1_LARB1_CKEN 0
|
||
|
|
#define CLK_VDE1_LAT_CKEN 1
|
||
|
|
#define CLK_VDE1_LAT_ACTIVE 2
|
||
|
|
#define CLK_VDE1_LAT_CKEN_ENG 3
|
||
|
|
#define CLK_VDE1_VDEC_CKEN 4
|
||
|
|
#define CLK_VDE1_VDEC_ACTIVE 5
|
||
|
|
#define CLK_VDE1_VDEC_CKEN_ENG 6
|
||
|
|
#define CLK_VDE1_NR_CLK 7
|
||
|
|
|
||
|
|
/* VDEC_GCON */
|
||
|
|
#define CLK_VDE2_LARB1_CKEN 0
|
||
|
|
#define CLK_VDE2_LAT_CKEN 1
|
||
|
|
#define CLK_VDE2_LAT_ACTIVE 2
|
||
|
|
#define CLK_VDE2_LAT_CKEN_ENG 3
|
||
|
|
#define CLK_VDE2_VDEC_CKEN 4
|
||
|
|
#define CLK_VDE2_VDEC_ACTIVE 5
|
||
|
|
#define CLK_VDE2_VDEC_CKEN_ENG 6
|
||
|
|
#define CLK_VDE2_NR_CLK 7
|
||
|
|
|
||
|
|
/* VENC_GCON */
|
||
|
|
#define CLK_VEN1_CKE0_LARB 0
|
||
|
|
#define CLK_VEN1_CKE1_VENC 1
|
||
|
|
#define CLK_VEN1_CKE2_JPGENC 2
|
||
|
|
#define CLK_VEN1_CKE3_JPGDEC 3
|
||
|
|
#define CLK_VEN1_CKE4_JPGDEC_C1 4
|
||
|
|
#define CLK_VEN1_CKE5_GALS 5
|
||
|
|
#define CLK_VEN1_NR_CLK 6
|
||
|
|
|
||
|
|
/* VENC_C1_GCON */
|
||
|
|
#define CLK_VEN2_CKE0_LARB 0
|
||
|
|
#define CLK_VEN2_CKE1_VENC 1
|
||
|
|
#define CLK_VEN2_CKE2_JPGENC 2
|
||
|
|
#define CLK_VEN2_CKE3_JPGDEC 3
|
||
|
|
#define CLK_VEN2_CKE4_JPGDEC_C1 4
|
||
|
|
#define CLK_VEN2_CKE5_GALS 5
|
||
|
|
#define CLK_VEN2_NR_CLK 6
|
||
|
|
|
||
|
|
/* APU_CONN */
|
||
|
|
#define CLK_APUC_AHB 0
|
||
|
|
#define CLK_APUC_AXI 1
|
||
|
|
#define CLK_APUC_ISP 2
|
||
|
|
#define CLK_APUC_CAM_ADL 3
|
||
|
|
#define CLK_APUC_IMG_ADL 4
|
||
|
|
#define CLK_APUC_EMI_26M 5
|
||
|
|
#define CLK_APUC_VPU_UDI 6
|
||
|
|
#define CLK_APUC_EDMA_0 7
|
||
|
|
#define CLK_APUC_EDMA_1 8
|
||
|
|
#define CLK_APUC_EDMAL_0 9
|
||
|
|
#define CLK_APUC_EDMAL_1 10
|
||
|
|
#define CLK_APUC_MNOC 11
|
||
|
|
#define CLK_APUC_TCM 12
|
||
|
|
#define CLK_APUC_MD32 13
|
||
|
|
#define CLK_APUC_IOMMU_0 14
|
||
|
|
#define CLK_APUC_IOMMU_1 15
|
||
|
|
#define CLK_APUC_MD32_32K 16
|
||
|
|
#define CLK_APUC_NR_CLK 17
|
||
|
|
|
||
|
|
/* APU_VCORE */
|
||
|
|
#define CLK_APUV_AHB 0
|
||
|
|
#define CLK_APUV_AXI 1
|
||
|
|
#define CLK_APUV_ADL 2
|
||
|
|
#define CLK_APUV_QOS 3
|
||
|
|
#define CLK_APUV_NR_CLK 4
|
||
|
|
|
||
|
|
/* APU0 */
|
||
|
|
#define CLK_APU0_APU 0
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||
|
|
#define CLK_APU0_AXI_M 1
|
||
|
|
#define CLK_APU0_JTAG 2
|
||
|
|
#define CLK_APU0_NR_CLK 3
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||
|
|
|
||
|
|
/* APU1 */
|
||
|
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#define CLK_APU1_APU 0
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||
|
|
#define CLK_APU1_AXI_M 1
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||
|
|
#define CLK_APU1_JTAG 2
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||
|
|
#define CLK_APU1_NR_CLK 3
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||
|
|
|
||
|
|
/* APU2 */
|
||
|
|
#define CLK_APU2_APU 0
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|
|
#define CLK_APU2_AXI_M 1
|
||
|
|
#define CLK_APU2_JTAG 2
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||
|
|
#define CLK_APU2_NR_CLK 3
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||
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|
|
||
|
|
/* APU_MDLA0 */
|
||
|
|
#define CLK_APUM0_MDLA_CG0 0
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||
|
|
#define CLK_APUM0_MDLA_CG1 1
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||
|
|
#define CLK_APUM0_MDLA_CG2 2
|
||
|
|
#define CLK_APUM0_MDLA_CG3 3
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||
|
|
#define CLK_APUM0_MDLA_CG4 4
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||
|
|
#define CLK_APUM0_MDLA_CG5 5
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||
|
|
#define CLK_APUM0_MDLA_CG6 6
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||
|
|
#define CLK_APUM0_MDLA_CG7 7
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||
|
|
#define CLK_APUM0_MDLA_CG8 8
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||
|
|
#define CLK_APUM0_MDLA_CG9 9
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||
|
|
#define CLK_APUM0_MDLA_CG10 10
|
||
|
|
#define CLK_APUM0_MDLA_CG11 11
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||
|
|
#define CLK_APUM0_MDLA_CG12 12
|
||
|
|
#define CLK_APUM0_APB 13
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||
|
|
#define CLK_APUM0_AXI_M 14
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||
|
|
#define CLK_APUM0_NR_CLK 15
|
||
|
|
|
||
|
|
/* APU_MDLA1 */
|
||
|
|
#define CLK_APUM1_MDLA_CG0 0
|
||
|
|
#define CLK_APUM1_MDLA_CG1 1
|
||
|
|
#define CLK_APUM1_MDLA_CG2 2
|
||
|
|
#define CLK_APUM1_MDLA_CG3 3
|
||
|
|
#define CLK_APUM1_MDLA_CG4 4
|
||
|
|
#define CLK_APUM1_MDLA_CG5 5
|
||
|
|
#define CLK_APUM1_MDLA_CG6 6
|
||
|
|
#define CLK_APUM1_MDLA_CG7 7
|
||
|
|
#define CLK_APUM1_MDLA_CG8 8
|
||
|
|
#define CLK_APUM1_MDLA_CG9 9
|
||
|
|
#define CLK_APUM1_MDLA_CG10 10
|
||
|
|
#define CLK_APUM1_MDLA_CG11 11
|
||
|
|
#define CLK_APUM1_MDLA_CG12 12
|
||
|
|
#define CLK_APUM1_APB 13
|
||
|
|
#define CLK_APUM1_AXI_M 14
|
||
|
|
#define CLK_APUM1_NR_CLK 15
|
||
|
|
|
||
|
|
/* CAMSYS_MAIN */
|
||
|
|
#define CLK_CAM_M_LARB13 0
|
||
|
|
#define CLK_CAM_M_DFP_VAD 1
|
||
|
|
#define CLK_CAM_M_LARB14 2
|
||
|
|
#define CLK_CAM_M_LARB15 3
|
||
|
|
#define CLK_CAM_M_CAM 4
|
||
|
|
#define CLK_CAM_M_CAMTG 5
|
||
|
|
#define CLK_CAM_M_SENINF 6
|
||
|
|
#define CLK_CAM_M_CAMSV0 7
|
||
|
|
#define CLK_CAM_M_CAMSV1 8
|
||
|
|
#define CLK_CAM_M_CAMSV2 9
|
||
|
|
#define CLK_CAM_M_CAMSV3 10
|
||
|
|
#define CLK_CAM_M_CCU0 11
|
||
|
|
#define CLK_CAM_M_CCU1 12
|
||
|
|
#define CLK_CAM_M_MRAW0 13
|
||
|
|
#define CLK_CAM_M_MRAW1 14
|
||
|
|
#define CLK_CAM_M_FAKE_ENG 15
|
||
|
|
#define CLK_CAM_M_NR_CLK 16
|
||
|
|
|
||
|
|
/* CAMSYS_RAWA */
|
||
|
|
#define CLK_CAM_RA_LARBX 0
|
||
|
|
#define CLK_CAM_RA_CAM 1
|
||
|
|
#define CLK_CAM_RA_CAMTG 2
|
||
|
|
#define CLK_CAM_RA_NR_CLK 3
|
||
|
|
|
||
|
|
/* CAMSYS_RAWB */
|
||
|
|
#define CLK_CAM_RB_LARBX 0
|
||
|
|
#define CLK_CAM_RB_CAM 1
|
||
|
|
#define CLK_CAM_RB_CAMTG 2
|
||
|
|
#define CLK_CAM_RB_NR_CLK 3
|
||
|
|
|
||
|
|
/* CAMSYS_RAWC */
|
||
|
|
#define CLK_CAM_RC_LARBX 0
|
||
|
|
#define CLK_CAM_RC_CAM 1
|
||
|
|
#define CLK_CAM_RC_CAMTG 2
|
||
|
|
#define CLK_CAM_RC_NR_CLK 3
|
||
|
|
|
||
|
|
/* IPESYS */
|
||
|
|
#define CLK_IPE_LARB19 0
|
||
|
|
#define CLK_IPE_LARB20 1
|
||
|
|
#define CLK_IPE_SMI_SUBCOM 2
|
||
|
|
#define CLK_IPE_FD 3
|
||
|
|
#define CLK_IPE_FE 4
|
||
|
|
#define CLK_IPE_RSC 5
|
||
|
|
#define CLK_IPE_DPE 6
|
||
|
|
#define CLK_IPE_NR_CLK 7
|
||
|
|
|
||
|
|
/* MDPSYS_CONFIG */
|
||
|
|
#define CLK_MDP_RDMA0 0
|
||
|
|
#define CLK_MDP_FG0 1
|
||
|
|
#define CLK_MDP_HDR0 2
|
||
|
|
#define CLK_MDP_AAL0 3
|
||
|
|
#define CLK_MDP_RSZ0 4
|
||
|
|
#define CLK_MDP_TDSHP0 5
|
||
|
|
#define CLK_MDP_TCC0 6
|
||
|
|
#define CLK_MDP_WROT0 7
|
||
|
|
#define CLK_MDP_RDMA2 8
|
||
|
|
#define CLK_MDP_AAL2 9
|
||
|
|
#define CLK_MDP_RSZ2 10
|
||
|
|
#define CLK_MDP_COLOR0 11
|
||
|
|
#define CLK_MDP_TDSHP2 12
|
||
|
|
#define CLK_MDP_TCC2 13
|
||
|
|
#define CLK_MDP_WROT2 14
|
||
|
|
#define CLK_MDP_MUTEX0 15
|
||
|
|
#define CLK_MDP_RDMA1 16
|
||
|
|
#define CLK_MDP_FG1 17
|
||
|
|
#define CLK_MDP_HDR1 18
|
||
|
|
#define CLK_MDP_AAL1 19
|
||
|
|
#define CLK_MDP_RSZ1 20
|
||
|
|
#define CLK_MDP_TDSHP1 21
|
||
|
|
#define CLK_MDP_TCC1 22
|
||
|
|
#define CLK_MDP_WROT1 23
|
||
|
|
#define CLK_MDP_RDMA3 24
|
||
|
|
#define CLK_MDP_AAL3 25
|
||
|
|
#define CLK_MDP_RSZ3 26
|
||
|
|
#define CLK_MDP_COLOR1 27
|
||
|
|
#define CLK_MDP_TDSHP3 28
|
||
|
|
#define CLK_MDP_TCC3 29
|
||
|
|
#define CLK_MDP_WROT3 30
|
||
|
|
#define CLK_MDP_APB_BUS 31
|
||
|
|
#define CLK_MDP_MMSYSRAM 32
|
||
|
|
#define CLK_MDP_APMCU_GALS 33
|
||
|
|
#define CLK_MDP_FAKE_ENG0 34
|
||
|
|
#define CLK_MDP_FAKE_ENG1 35
|
||
|
|
#define CLK_MDP_SMI0 36
|
||
|
|
#define CLK_MDP_IMG_DL_ASYNC0 37
|
||
|
|
#define CLK_MDP_IMG_DL_ASYNC1 38
|
||
|
|
#define CLK_MDP_IMG_DL_ASYNC2 39
|
||
|
|
#define CLK_MDP_SMI1 40
|
||
|
|
#define CLK_MDP_IMG_DL_ASYNC3 41
|
||
|
|
#define CLK_MDP_RESERVED42 42
|
||
|
|
#define CLK_MDP_RESERVED43 43
|
||
|
|
#define CLK_MDP_SMI2 44
|
||
|
|
#define CLK_MDP_RESERVED45 45
|
||
|
|
#define CLK_MDP_RESERVED46 46
|
||
|
|
#define CLK_MDP_RESERVED47 47
|
||
|
|
#define CLK_MDP_IMG0_IMG_DL_ASYNC0 48
|
||
|
|
#define CLK_MDP_IMG0_IMG_DL_ASYNC1 49
|
||
|
|
#define CLK_MDP_IMG1_IMG_DL_ASYNC2 50
|
||
|
|
#define CLK_MDP_IMG1_IMG_DL_ASYNC3 51
|
||
|
|
#define CLK_MDP_NR_CLK 52
|
||
|
|
|
||
|
|
/* SCP_SYS */
|
||
|
|
#define SCP_SYS_MD1 0
|
||
|
|
#define SCP_SYS_CONN 1
|
||
|
|
#define SCP_SYS_MFG0 2
|
||
|
|
#define SCP_SYS_MFG1 3
|
||
|
|
#define SCP_SYS_MFG2 4
|
||
|
|
#define SCP_SYS_MFG3 5
|
||
|
|
#define SCP_SYS_MFG4 6
|
||
|
|
#define SCP_SYS_MFG5 7
|
||
|
|
#define SCP_SYS_MFG6 8
|
||
|
|
#define SCP_SYS_IFR 9
|
||
|
|
#define SCP_SYS_IFR_SUB 10
|
||
|
|
#define SCP_SYS_DPY 11
|
||
|
|
#define SCP_SYS_ISP 12
|
||
|
|
#define SCP_SYS_ISP2 13
|
||
|
|
#define SCP_SYS_IPE 14
|
||
|
|
#define SCP_SYS_VDEC 15
|
||
|
|
#define SCP_SYS_VDEC2 16
|
||
|
|
#define SCP_SYS_VENC 17
|
||
|
|
#define SCP_SYS_VENC_CORE1 18
|
||
|
|
#define SCP_SYS_MDP 19
|
||
|
|
#define SCP_SYS_DIS 20
|
||
|
|
#define SCP_SYS_AUDIO 21
|
||
|
|
#define SCP_SYS_ADSP 22
|
||
|
|
#define SCP_SYS_CAM 23
|
||
|
|
#define SCP_SYS_CAM_RAWA 24
|
||
|
|
#define SCP_SYS_CAM_RAWB 25
|
||
|
|
#define SCP_SYS_CAM_RAWC 26
|
||
|
|
#define SCP_SYS_DP_TX 27
|
||
|
|
#define SCP_SYS_DPY2 28
|
||
|
|
#define SCP_SYS_VPU 29
|
||
|
|
#define SCP_NR_SYSS 30
|
||
|
|
|
||
|
|
#endif /* _DT_BINDINGS_CLK_MT6893_H */
|