78 lines
3.1 KiB
Plaintext
78 lines
3.1 KiB
Plaintext
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Device Tree Bindings for the Arasan SDHCI Controller
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The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
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Only deviations are documented here.
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[1] Documentation/devicetree/bindings/mmc/mmc.txt
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[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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[4] Documentation/devicetree/bindings/phy/phy-bindings.txt
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Required Properties:
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- compatible: Compatibility string. One of:
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- "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
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- "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
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- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
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- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
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For this device it is strongly suggested to include arasan,soc-ctl-syscon.
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- reg: From mmc bindings: Register location and length.
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- clocks: From clock bindings: Handles to clock inputs.
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- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
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- interrupts: Interrupt specifier
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Required Properties for "arasan,sdhci-5.1":
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- phys: From PHY bindings: Phandle for the Generic PHY for arasan.
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- phy-names: MUST be "phy_arasan".
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Optional Properties:
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- arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
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used to access core corecfg registers. Offsets of registers in this
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syscon are determined based on the main compatible string for the device.
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- clock-output-names: If specified, this will be the name of the card clock
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which will be exposed by this device. Required if #clock-cells is
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specified.
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- #clock-cells: If specified this should be the value <0>. With this property
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in place we will export a clock representing the Card Clock. This clock
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is expected to be consumed by our PHY. You must also specify
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- xlnx,fails-without-test-cd: when present, the controller doesn't work when
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the CD line is not connected properly, and the line is not connected
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properly. Test mode can be used to force the controller to function.
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- xlnx,int-clock-stable-broken: when present, the controller always reports
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that the internal clock is stable even when it is not.
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Example:
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sdhci@e0100000 {
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compatible = "arasan,sdhci-8.9a";
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reg = <0xe0100000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkc 21>, <&clkc 32>;
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interrupt-parent = <&gic>;
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interrupts = <0 24 4>;
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} ;
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sdhci@e2800000 {
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compatible = "arasan,sdhci-5.1";
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reg = <0xe2800000 0x1000>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&cru 8>, <&cru 18>;
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interrupt-parent = <&gic>;
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interrupts = <0 24 4>;
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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} ;
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sdhci: sdhci@fe330000 {
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compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
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reg = <0x0 0xfe330000 0x0 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
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clock-names = "clk_xin", "clk_ahb";
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arasan,soc-ctl-syscon = <&grf>;
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assigned-clocks = <&cru SCLK_EMMC>;
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assigned-clock-rates = <200000000>;
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clock-output-names = "emmc_cardclock";
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phys = <&emmc_phy>;
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phy-names = "phy_arasan";
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#clock-cells = <0>;
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};
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