81 lines
2.8 KiB
Plaintext
81 lines
2.8 KiB
Plaintext
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* Cadence SD/SDIO/eMMC Host Controller
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Required properties:
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- compatible: should be one of the following:
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"cdns,sd4hc" - default of the IP
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"socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs
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- reg: offset and length of the register set for the device.
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- interrupts: a single interrupt specifier.
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- clocks: phandle to the input clock.
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Optional properties:
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For eMMC configuration, supported speed modes are not indicated by the SDHCI
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Capabilities Register. Instead, the following properties should be specified
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if supported. See mmc.txt for details.
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- mmc-ddr-1_8v
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- mmc-ddr-1_2v
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- mmc-hs200-1_8v
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- mmc-hs200-1_2v
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- mmc-hs400-1_8v
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- mmc-hs400-1_2v
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Some PHY delays can be configured by following properties.
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PHY DLL input delays:
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They are used to delay the data valid window, and align the window
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to sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
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and it is increased by 2.5ns in each step.
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- cdns,phy-input-delay-sd-highspeed:
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Value of the delay in the input path for SD high-speed timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-legacy:
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Value of the delay in the input path for legacy timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-sd-uhs-sdr12:
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Value of the delay in the input path for SD UHS SDR12 timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-sd-uhs-sdr25:
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Value of the delay in the input path for SD UHS SDR25 timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-sd-uhs-sdr50:
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Value of the delay in the input path for SD UHS SDR50 timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-sd-uhs-ddr50:
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Value of the delay in the input path for SD UHS DDR50 timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-mmc-highspeed:
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Value of the delay in the input path for MMC high-speed timing
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Valid range = [0:0x1F].
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- cdns,phy-input-delay-mmc-ddr:
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Value of the delay in the input path for eMMC high-speed DDR timing
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Valid range = [0:0x1F].
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PHY DLL clock delays:
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Each delay property represents the fraction of the clock period.
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The approximate delay value will be
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(<delay property value>/128)*sdmclk_clock_period.
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- cdns,phy-dll-delay-sdclk:
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Value of the delay introduced on the sdclk output
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for all modes except HS200, HS400 and HS400_ES.
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Valid range = [0:0x7F].
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- cdns,phy-dll-delay-sdclk-hsmmc:
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Value of the delay introduced on the sdclk output
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for HS200, HS400 and HS400_ES speed modes.
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Valid range = [0:0x7F].
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- cdns,phy-dll-delay-strobe:
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Value of the delay introduced on the dat_strobe input
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used in HS400 / HS400_ES speed modes.
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Valid range = [0:0x7F].
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Example:
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emmc: sdhci@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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clocks = <&clk 4>;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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cdns,phy-dll-delay-sdclk = <0>;
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};
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