28 lines
1,004 B
Plaintext
28 lines
1,004 B
Plaintext
|
Freescale i.MX PWM controller
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible : should be "fsl,<soc>-pwm" and one of the following
|
||
|
|
compatible strings:
|
||
|
|
- "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1
|
||
|
|
- "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27
|
||
|
|
- reg: physical base address and length of the controller's registers
|
||
|
|
- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.txt
|
||
|
|
in this directory for a description of the cells format.
|
||
|
|
- clocks : Clock specifiers for both ipg and per clocks.
|
||
|
|
- clock-names : Clock names should include both "ipg" and "per"
|
||
|
|
See the clock consumer binding,
|
||
|
|
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||
|
|
- interrupts: The interrupt for the pwm controller
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
pwm1: pwm@53fb4000 {
|
||
|
|
#pwm-cells = <3>;
|
||
|
|
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||
|
|
reg = <0x53fb4000 0x4000>;
|
||
|
|
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||
|
|
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||
|
|
clock-names = "ipg", "per";
|
||
|
|
interrupts = <61>;
|
||
|
|
};
|