341 lines
10 KiB
C
341 lines
10 KiB
C
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/*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2010 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Corporation
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* 2200 Mission College Blvd.
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* Santa Clara, CA 97052
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*
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* This provides access methods for PCI registers that mis-behave on
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* the CE4100. Each register can be assigned a private init, read and
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* write routine. The exception to this is the bridge device. The
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* bridge device is the only device on bus zero (0) that requires any
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* fixup so it is a special case ATM
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/ce4100.h>
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#include <asm/pci_x86.h>
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struct sim_reg {
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u32 value;
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u32 mask;
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};
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struct sim_dev_reg {
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int dev_func;
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int reg;
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void (*init)(struct sim_dev_reg *reg);
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void (*read)(struct sim_dev_reg *reg, u32 *value);
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void (*write)(struct sim_dev_reg *reg, u32 value);
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struct sim_reg sim_reg;
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};
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struct sim_reg_op {
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void (*init)(struct sim_dev_reg *reg);
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void (*read)(struct sim_dev_reg *reg, u32 value);
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void (*write)(struct sim_dev_reg *reg, u32 value);
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};
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#define MB (1024 * 1024)
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#define KB (1024)
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#define SIZE_TO_MASK(size) (~(size - 1))
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#define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\
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{ PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\
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{0, SIZE_TO_MASK(size)} },
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/*
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* All read/write functions are called with pci_config_lock held.
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*/
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static void reg_init(struct sim_dev_reg *reg)
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{
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pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,
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®->sim_reg.value);
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}
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static void reg_read(struct sim_dev_reg *reg, u32 *value)
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{
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*value = reg->sim_reg.value;
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}
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static void reg_write(struct sim_dev_reg *reg, u32 value)
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{
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reg->sim_reg.value = (value & reg->sim_reg.mask) |
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(reg->sim_reg.value & ~reg->sim_reg.mask);
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}
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static void sata_reg_init(struct sim_dev_reg *reg)
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{
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pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,
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®->sim_reg.value);
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reg->sim_reg.value += 0x400;
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}
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static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value)
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{
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reg_read(reg, value);
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if (*value != reg->sim_reg.mask)
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*value |= 0x100;
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}
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void sata_revid_init(struct sim_dev_reg *reg)
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{
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reg->sim_reg.value = 0x01060100;
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reg->sim_reg.mask = 0;
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}
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static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
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{
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reg_read(reg, value);
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}
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static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value)
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{
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/* force interrupt pin value to 0 */
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*value = reg->sim_reg.value & 0xfff00ff;
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}
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static struct sim_dev_reg bus1_fixups[] = {
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DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
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DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
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DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
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DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
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DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
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DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
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DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
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DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
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DEFINE_REG(14, 0, 0x8, 0, sata_revid_init, sata_revid_read, 0)
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DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
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DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
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DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
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DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
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DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
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DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
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DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
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DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
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DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
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DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
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DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
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};
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static void __init init_sim_regs(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
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if (bus1_fixups[i].init)
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bus1_fixups[i].init(&bus1_fixups[i]);
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}
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}
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static inline void extract_bytes(u32 *value, int reg, int len)
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{
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uint32_t mask;
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*value >>= ((reg & 3) * 8);
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mask = 0xFFFFFFFF >> ((4 - len) * 8);
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*value &= mask;
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}
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int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
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{
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u32 av_bridge_base, av_bridge_limit;
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int retval = 0;
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switch (reg) {
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/* Make BARs appear to not request any memory. */
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_0 + 1:
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case PCI_BASE_ADDRESS_0 + 2:
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case PCI_BASE_ADDRESS_0 + 3:
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*value = 0;
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break;
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/* Since subordinate bus number register is hardwired
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* to zero and read only, so do the simulation.
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*/
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case PCI_PRIMARY_BUS:
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if (len == 4)
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*value = 0x00010100;
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break;
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case PCI_SUBORDINATE_BUS:
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*value = 1;
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break;
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case PCI_MEMORY_BASE:
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case PCI_MEMORY_LIMIT:
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/* Get the A/V bridge base address. */
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pci_direct_conf1.read(0, 0, devfn,
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PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
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av_bridge_limit = av_bridge_base + (512*MB - 1);
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av_bridge_limit >>= 16;
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av_bridge_limit &= 0xFFF0;
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av_bridge_base >>= 16;
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av_bridge_base &= 0xFFF0;
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if (reg == PCI_MEMORY_LIMIT)
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*value = av_bridge_limit;
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else if (len == 2)
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*value = av_bridge_base;
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else
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*value = (av_bridge_limit << 16) | av_bridge_base;
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break;
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/* Make prefetchable memory limit smaller than prefetchable
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* memory base, so not claim prefetchable memory space.
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*/
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case PCI_PREF_MEMORY_BASE:
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*value = 0xFFF0;
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break;
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case PCI_PREF_MEMORY_LIMIT:
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*value = 0x0;
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break;
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/* Make IO limit smaller than IO base, so not claim IO space. */
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case PCI_IO_BASE:
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*value = 0xF0;
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break;
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case PCI_IO_LIMIT:
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*value = 0;
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break;
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default:
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retval = 1;
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}
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return retval;
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}
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static int ce4100_bus1_read(unsigned int devfn, int reg, int len, u32 *value)
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{
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unsigned long flags;
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int i;
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for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
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if (bus1_fixups[i].dev_func == devfn &&
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bus1_fixups[i].reg == (reg & ~3) &&
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bus1_fixups[i].read) {
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raw_spin_lock_irqsave(&pci_config_lock, flags);
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bus1_fixups[i].read(&(bus1_fixups[i]), value);
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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extract_bytes(value, reg, len);
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return 0;
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}
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}
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return -1;
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}
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static int ce4100_conf_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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WARN_ON(seg);
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if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value))
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return 0;
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if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
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!bridge_read(devfn, reg, len, value))
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return 0;
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return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
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}
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static int ce4100_bus1_write(unsigned int devfn, int reg, int len, u32 value)
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{
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unsigned long flags;
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int i;
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for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
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if (bus1_fixups[i].dev_func == devfn &&
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bus1_fixups[i].reg == (reg & ~3) &&
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bus1_fixups[i].write) {
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raw_spin_lock_irqsave(&pci_config_lock, flags);
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bus1_fixups[i].write(&(bus1_fixups[i]), value);
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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}
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return -1;
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}
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static int ce4100_conf_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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WARN_ON(seg);
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if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value))
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return 0;
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/* Discard writes to A/V bridge BAR. */
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if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
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((reg & ~3) == PCI_BASE_ADDRESS_0))
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return 0;
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return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
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}
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static const struct pci_raw_ops ce4100_pci_conf = {
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.read = ce4100_conf_read,
|
||
|
|
.write = ce4100_conf_write,
|
||
|
|
};
|
||
|
|
|
||
|
|
int __init ce4100_pci_init(void)
|
||
|
|
{
|
||
|
|
init_sim_regs();
|
||
|
|
raw_pci_ops = &ce4100_pci_conf;
|
||
|
|
/* Indicate caller that it should invoke pci_legacy_init() */
|
||
|
|
return 1;
|
||
|
|
}
|