202 lines
7.1 KiB
C
202 lines
7.1 KiB
C
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/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jim Liu <jim.liu@intel.com>
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* Jackie Li<yaodong.li@intel.com>
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* Gideon Eaton <eaton.
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* Scott Rowe <scott.m.rowe@intel.com>
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*/
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#include "mdfld_dsi_dpi.h"
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#include "mdfld_dsi_pkg_sender.h"
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static struct drm_display_mode *tmd_vid_get_config_mode(struct drm_device *dev)
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{
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struct drm_display_mode *mode;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
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bool use_gct = false; /*Disable GCT for now*/
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mode = kzalloc(sizeof(*mode), GFP_KERNEL);
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if (!mode)
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return NULL;
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if (use_gct) {
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mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
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mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
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mode->hsync_start = mode->hdisplay + \
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((ti->hsync_offset_hi << 8) | \
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ti->hsync_offset_lo);
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mode->hsync_end = mode->hsync_start + \
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((ti->hsync_pulse_width_hi << 8) | \
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ti->hsync_pulse_width_lo);
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mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
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ti->hblank_lo);
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mode->vsync_start = \
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mode->vdisplay + ((ti->vsync_offset_hi << 8) | \
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ti->vsync_offset_lo);
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mode->vsync_end = \
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mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) | \
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ti->vsync_pulse_width_lo);
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mode->vtotal = mode->vdisplay + \
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((ti->vblank_hi << 8) | ti->vblank_lo);
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mode->clock = ti->pixel_clock * 10;
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dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
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dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
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dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
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dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
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dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
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dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
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dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
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dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
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dev_dbg(dev->dev, "clock is %d\n", mode->clock);
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} else {
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mode->hdisplay = 480;
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mode->vdisplay = 854;
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mode->hsync_start = 487;
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mode->hsync_end = 490;
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mode->htotal = 499;
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mode->vsync_start = 861;
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mode->vsync_end = 865;
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mode->vtotal = 873;
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mode->clock = 33264;
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}
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drm_mode_set_name(mode);
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drm_mode_set_crtcinfo(mode, 0);
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mode->type |= DRM_MODE_TYPE_PREFERRED;
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return mode;
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}
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static int tmd_vid_get_panel_info(struct drm_device *dev,
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int pipe,
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struct panel_info *pi)
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{
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if (!dev || !pi)
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return -EINVAL;
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pi->width_mm = TMD_PANEL_WIDTH;
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pi->height_mm = TMD_PANEL_HEIGHT;
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return 0;
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}
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/* ************************************************************************* *\
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* FUNCTION: mdfld_init_TMD_MIPI
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*
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* DESCRIPTION: This function is called only by mrst_dsi_mode_set and
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* restore_display_registers. since this function does not
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* acquire the mutex, it is important that the calling function
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* does!
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\* ************************************************************************* */
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/* FIXME: make the below data u8 instead of u32; note byte order! */
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static u32 tmd_cmd_mcap_off[] = {0x000000b2};
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static u32 tmd_cmd_enable_lane_switch[] = {0x000101ef};
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static u32 tmd_cmd_set_lane_num[] = {0x006360ef};
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static u32 tmd_cmd_pushing_clock0[] = {0x00cc2fef};
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static u32 tmd_cmd_pushing_clock1[] = {0x00dd6eef};
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static u32 tmd_cmd_set_mode[] = {0x000000b3};
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static u32 tmd_cmd_set_sync_pulse_mode[] = {0x000961ef};
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static u32 tmd_cmd_set_column[] = {0x0100002a, 0x000000df};
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static u32 tmd_cmd_set_page[] = {0x0300002b, 0x00000055};
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static u32 tmd_cmd_set_video_mode[] = {0x00000153};
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/*no auto_bl,need add in furture*/
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static u32 tmd_cmd_enable_backlight[] = {0x00005ab4};
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static u32 tmd_cmd_set_backlight_dimming[] = {0x00000ebd};
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static void mdfld_dsi_tmd_drv_ic_init(struct mdfld_dsi_config *dsi_config,
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int pipe)
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{
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struct mdfld_dsi_pkg_sender *sender
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= mdfld_dsi_get_pkg_sender(dsi_config);
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DRM_INFO("Enter mdfld init TMD MIPI display.\n");
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if (!sender) {
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DRM_ERROR("Cannot get sender\n");
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return;
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}
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if (dsi_config->dvr_ic_inited)
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return;
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msleep(3);
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/* FIXME: make the below data u8 instead of u32; note byte order! */
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_mcap_off,
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sizeof(tmd_cmd_mcap_off), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_enable_lane_switch,
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sizeof(tmd_cmd_enable_lane_switch), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_lane_num,
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sizeof(tmd_cmd_set_lane_num), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_pushing_clock0,
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sizeof(tmd_cmd_pushing_clock0), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_pushing_clock1,
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sizeof(tmd_cmd_pushing_clock1), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_mode,
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sizeof(tmd_cmd_set_mode), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_sync_pulse_mode,
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sizeof(tmd_cmd_set_sync_pulse_mode), false);
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mdfld_dsi_send_mcs_long(sender, (u8 *) tmd_cmd_set_column,
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sizeof(tmd_cmd_set_column), false);
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mdfld_dsi_send_mcs_long(sender, (u8 *) tmd_cmd_set_page,
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sizeof(tmd_cmd_set_page), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_video_mode,
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sizeof(tmd_cmd_set_video_mode), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_enable_backlight,
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sizeof(tmd_cmd_enable_backlight), false);
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mdfld_dsi_send_gen_long(sender, (u8 *) tmd_cmd_set_backlight_dimming,
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sizeof(tmd_cmd_set_backlight_dimming), false);
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dsi_config->dvr_ic_inited = 1;
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}
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/*TPO DPI encoder helper funcs*/
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static const struct drm_encoder_helper_funcs
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mdfld_tpo_dpi_encoder_helper_funcs = {
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.dpms = mdfld_dsi_dpi_dpms,
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.mode_fixup = mdfld_dsi_dpi_mode_fixup,
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.prepare = mdfld_dsi_dpi_prepare,
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.mode_set = mdfld_dsi_dpi_mode_set,
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.commit = mdfld_dsi_dpi_commit,
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};
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/*TPO DPI encoder funcs*/
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static const struct drm_encoder_funcs mdfld_tpo_dpi_encoder_funcs = {
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.destroy = drm_encoder_cleanup,
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};
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const struct panel_funcs mdfld_tmd_vid_funcs = {
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.encoder_funcs = &mdfld_tpo_dpi_encoder_funcs,
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.encoder_helper_funcs = &mdfld_tpo_dpi_encoder_helper_funcs,
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.get_config_mode = &tmd_vid_get_config_mode,
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.get_panel_info = tmd_vid_get_panel_info,
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.reset = mdfld_dsi_panel_reset,
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.drv_ic_init = mdfld_dsi_tmd_drv_ic_init,
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};
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