140 lines
3.3 KiB
C
140 lines
3.3 KiB
C
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/*
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* SMP support for J2 processor
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*
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* Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/cmpxchg.h>
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DEFINE_PER_CPU(unsigned, j2_ipi_messages);
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extern u32 *sh2_cpuid_addr;
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static u32 *j2_ipi_trigger;
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static int j2_ipi_irq;
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static irqreturn_t j2_ipi_interrupt_handler(int irq, void *arg)
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{
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unsigned cpu = hard_smp_processor_id();
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volatile unsigned *pmsg = &per_cpu(j2_ipi_messages, cpu);
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unsigned messages, i;
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do messages = *pmsg;
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while (cmpxchg(pmsg, messages, 0) != messages);
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if (!messages) return IRQ_NONE;
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for (i=0; i<SMP_MSG_NR; i++)
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if (messages & (1U<<i))
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smp_message_recv(i);
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return IRQ_HANDLED;
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}
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static void j2_smp_setup(void)
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{
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}
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static void j2_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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unsigned i, max = 1;
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np = of_find_compatible_node(NULL, NULL, "jcore,ipi-controller");
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if (!np)
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goto out;
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j2_ipi_irq = irq_of_parse_and_map(np, 0);
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j2_ipi_trigger = of_iomap(np, 0);
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if (!j2_ipi_irq || !j2_ipi_trigger)
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goto out;
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np = of_find_compatible_node(NULL, NULL, "jcore,cpuid-mmio");
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if (!np)
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goto out;
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sh2_cpuid_addr = of_iomap(np, 0);
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if (!sh2_cpuid_addr)
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goto out;
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if (request_irq(j2_ipi_irq, j2_ipi_interrupt_handler, IRQF_PERCPU,
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"ipi", (void *)j2_ipi_interrupt_handler) != 0)
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goto out;
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max = max_cpus;
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out:
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/* Disable any cpus past max_cpus, or all secondaries if we didn't
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* get the necessary resources to support SMP. */
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for (i=max; i<NR_CPUS; i++) {
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set_cpu_possible(i, false);
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set_cpu_present(i, false);
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}
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}
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static void j2_start_cpu(unsigned int cpu, unsigned long entry_point)
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{
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struct device_node *np;
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u32 regs[2];
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void __iomem *release, *initpc;
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if (!cpu) return;
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np = of_get_cpu_node(cpu, NULL);
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if (!np) return;
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if (of_property_read_u32_array(np, "cpu-release-addr", regs, 2)) return;
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release = ioremap_nocache(regs[0], sizeof(u32));
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initpc = ioremap_nocache(regs[1], sizeof(u32));
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__raw_writel(entry_point, initpc);
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__raw_writel(1, release);
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iounmap(initpc);
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iounmap(release);
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pr_info("J2 SMP: requested start of cpu %u\n", cpu);
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}
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static unsigned int j2_smp_processor_id(void)
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{
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return __raw_readl(sh2_cpuid_addr);
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}
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static void j2_send_ipi(unsigned int cpu, unsigned int message)
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{
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volatile unsigned *pmsg;
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unsigned old;
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unsigned long val;
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/* There is only one IPI interrupt shared by all messages, so
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* we keep a separate interrupt flag per message type in sw. */
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pmsg = &per_cpu(j2_ipi_messages, cpu);
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do old = *pmsg;
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while (cmpxchg(pmsg, old, old|(1U<<message)) != old);
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/* Generate the actual interrupt by writing to CCRn bit 28. */
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val = __raw_readl(j2_ipi_trigger + cpu);
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__raw_writel(val | (1U<<28), j2_ipi_trigger + cpu);
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}
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static struct plat_smp_ops j2_smp_ops = {
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.smp_setup = j2_smp_setup,
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.prepare_cpus = j2_prepare_cpus,
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.start_cpu = j2_start_cpu,
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.smp_processor_id = j2_smp_processor_id,
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.send_ipi = j2_send_ipi,
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.cpu_die = native_cpu_die,
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.cpu_disable = native_cpu_disable,
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.play_dead = native_play_dead,
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};
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CPU_METHOD_OF_DECLARE(j2_cpu_method, "jcore,spin-table", &j2_smp_ops);
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