284 lines
8.1 KiB
C
284 lines
8.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Meson GXL USB3 PHY and OTG mode detection driver
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*
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* Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#define USB_R0 0x00
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#define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
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#define USB_R0_P30_PHY_RESET BIT(6)
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#define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
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#define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
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#define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
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#define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
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#define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
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#define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
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#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
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#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
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#define USB_R0_U2D_ACT BIT(31)
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#define USB_R1 0x04
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#define USB_R1_U3H_BIGENDIAN_GS BIT(0)
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#define USB_R1_U3H_PME_ENABLE BIT(1)
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#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
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#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
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#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
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#define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
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#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
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#define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
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#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
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#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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#define USB_R2 0x08
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#define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
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#define USB_R2_P30_CR_READ BIT(16)
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#define USB_R2_P30_CR_WRITE BIT(17)
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#define USB_R2_P30_CR_CAP_ADDR BIT(18)
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#define USB_R2_P30_CR_CAP_DATA BIT(19)
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#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
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#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
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#define USB_R3 0x0c
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#define USB_R3_P30_SSC_ENABLE BIT(0)
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#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
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#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
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#define USB_R3_P30_REF_SSP_EN BIT(13)
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#define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
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#define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
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#define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
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#define USB_R4 0x10
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#define USB_R4_P21_PORT_RESET_0 BIT(0)
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#define USB_R4_P21_SLEEP_M0 BIT(1)
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#define USB_R4_MEM_PD_MASK GENMASK(3, 2)
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#define USB_R4_P21_ONLY BIT(4)
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#define USB_R5 0x14
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#define USB_R5_ID_DIG_SYNC BIT(0)
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#define USB_R5_ID_DIG_REG BIT(1)
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#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
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#define USB_R5_ID_DIG_EN_0 BIT(4)
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#define USB_R5_ID_DIG_EN_1 BIT(5)
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#define USB_R5_ID_DIG_CURR BIT(6)
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#define USB_R5_ID_DIG_IRQ BIT(7)
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#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
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#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
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/* read-only register */
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#define USB_R6 0x18
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#define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
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#define USB_R6_P30_CR_ACK BIT(16)
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struct phy_meson_gxl_usb3_priv {
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struct regmap *regmap;
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enum phy_mode mode;
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struct clk *clk_phy;
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struct clk *clk_peripheral;
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struct reset_control *reset;
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};
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static const struct regmap_config phy_meson_gxl_usb3_regmap_conf = {
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.reg_bits = 8,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = USB_R6,
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};
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static int phy_meson_gxl_usb3_power_on(struct phy *phy)
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{
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struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
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regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0,
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USB_R5_ID_DIG_EN_0);
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regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1,
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USB_R5_ID_DIG_EN_1);
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regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_TH_MASK,
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FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
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return 0;
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}
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static int phy_meson_gxl_usb3_power_off(struct phy *phy)
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{
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struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
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regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_0, 0);
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regmap_update_bits(priv->regmap, USB_R5, USB_R5_ID_DIG_EN_1, 0);
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return 0;
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}
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static int phy_meson_gxl_usb3_set_mode(struct phy *phy,
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enum phy_mode mode, int submode)
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{
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struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
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switch (mode) {
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case PHY_MODE_USB_HOST:
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regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT, 0);
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regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0,
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0);
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break;
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case PHY_MODE_USB_DEVICE:
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regmap_update_bits(priv->regmap, USB_R0, USB_R0_U2D_ACT,
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USB_R0_U2D_ACT);
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regmap_update_bits(priv->regmap, USB_R4, USB_R4_P21_SLEEP_M0,
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USB_R4_P21_SLEEP_M0);
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break;
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default:
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dev_err(&phy->dev, "unsupported PHY mode %d\n", mode);
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return -EINVAL;
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}
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priv->mode = mode;
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return 0;
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}
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static int phy_meson_gxl_usb3_init(struct phy *phy)
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{
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struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = reset_control_reset(priv->reset);
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if (ret)
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goto err;
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ret = clk_prepare_enable(priv->clk_phy);
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if (ret)
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goto err;
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ret = clk_prepare_enable(priv->clk_peripheral);
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if (ret)
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goto err_disable_clk_phy;
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ret = phy_meson_gxl_usb3_set_mode(phy, priv->mode, 0);
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if (ret)
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goto err_disable_clk_peripheral;
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regmap_update_bits(priv->regmap, USB_R1,
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USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
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FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
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return 0;
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err_disable_clk_peripheral:
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clk_disable_unprepare(priv->clk_peripheral);
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err_disable_clk_phy:
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clk_disable_unprepare(priv->clk_phy);
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err:
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return ret;
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}
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static int phy_meson_gxl_usb3_exit(struct phy *phy)
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{
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struct phy_meson_gxl_usb3_priv *priv = phy_get_drvdata(phy);
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clk_disable_unprepare(priv->clk_peripheral);
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clk_disable_unprepare(priv->clk_phy);
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return 0;
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}
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static const struct phy_ops phy_meson_gxl_usb3_ops = {
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.power_on = phy_meson_gxl_usb3_power_on,
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.power_off = phy_meson_gxl_usb3_power_off,
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.set_mode = phy_meson_gxl_usb3_set_mode,
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.init = phy_meson_gxl_usb3_init,
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.exit = phy_meson_gxl_usb3_exit,
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.owner = THIS_MODULE,
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};
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static int phy_meson_gxl_usb3_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct phy_meson_gxl_usb3_priv *priv;
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struct resource *res;
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struct phy *phy;
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struct phy_provider *phy_provider;
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void __iomem *base;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->regmap = devm_regmap_init_mmio(dev, base,
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&phy_meson_gxl_usb3_regmap_conf);
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if (IS_ERR(priv->regmap))
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return PTR_ERR(priv->regmap);
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priv->clk_phy = devm_clk_get(dev, "phy");
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if (IS_ERR(priv->clk_phy))
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return PTR_ERR(priv->clk_phy);
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priv->clk_peripheral = devm_clk_get(dev, "peripheral");
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if (IS_ERR(priv->clk_peripheral))
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return PTR_ERR(priv->clk_peripheral);
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priv->reset = devm_reset_control_array_get_shared(dev);
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if (IS_ERR(priv->reset))
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return PTR_ERR(priv->reset);
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/*
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* default to host mode as hardware defaults and/or boot-loader
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* behavior can result in this PHY starting up in device mode. this
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* default and the initialization in phy_meson_gxl_usb3_init ensure
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* that we reproducibly start in a known mode on all devices.
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*/
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priv->mode = PHY_MODE_USB_HOST;
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phy = devm_phy_create(dev, np, &phy_meson_gxl_usb3_ops);
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if (IS_ERR(phy)) {
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ret = PTR_ERR(phy);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "failed to create PHY\n");
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return ret;
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}
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phy_set_drvdata(phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id phy_meson_gxl_usb3_of_match[] = {
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{ .compatible = "amlogic,meson-gxl-usb3-phy", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb3_of_match);
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static struct platform_driver phy_meson_gxl_usb3_driver = {
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.probe = phy_meson_gxl_usb3_probe,
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.driver = {
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.name = "phy-meson-gxl-usb3",
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.of_match_table = phy_meson_gxl_usb3_of_match,
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},
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};
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module_platform_driver(phy_meson_gxl_usb3_driver);
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_DESCRIPTION("Meson GXL USB3 PHY and OTG detection driver");
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MODULE_LICENSE("GPL v2");
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