492 lines
11 KiB
C
492 lines
11 KiB
C
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/* cg3.c: CGTHREE frame buffer driver
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*
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* Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
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*
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* Driver layout based loosely on tgafb.c, see that file for credits.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/fb.h>
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#include <linux/mm.h>
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#include <linux/of_device.h>
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#include <asm/io.h>
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#include <asm/fbio.h>
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#include "sbuslib.h"
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/*
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* Local functions.
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*/
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static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
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unsigned, struct fb_info *);
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static int cg3_blank(int, struct fb_info *);
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static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
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static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
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/*
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* Frame buffer operations
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*/
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static struct fb_ops cg3_ops = {
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.owner = THIS_MODULE,
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.fb_setcolreg = cg3_setcolreg,
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.fb_blank = cg3_blank,
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.fb_fillrect = cfb_fillrect,
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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.fb_mmap = cg3_mmap,
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.fb_ioctl = cg3_ioctl,
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#ifdef CONFIG_COMPAT
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.fb_compat_ioctl = sbusfb_compat_ioctl,
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#endif
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};
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/* Control Register Constants */
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#define CG3_CR_ENABLE_INTS 0x80
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#define CG3_CR_ENABLE_VIDEO 0x40
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#define CG3_CR_ENABLE_TIMING 0x20
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#define CG3_CR_ENABLE_CURCMP 0x10
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#define CG3_CR_XTAL_MASK 0x0c
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#define CG3_CR_DIVISOR_MASK 0x03
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/* Status Register Constants */
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#define CG3_SR_PENDING_INT 0x80
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#define CG3_SR_RES_MASK 0x70
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#define CG3_SR_1152_900_76_A 0x40
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#define CG3_SR_1152_900_76_B 0x60
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#define CG3_SR_ID_MASK 0x0f
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#define CG3_SR_ID_COLOR 0x01
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#define CG3_SR_ID_MONO 0x02
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#define CG3_SR_ID_MONO_ECL 0x03
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enum cg3_type {
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CG3_AT_66HZ = 0,
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CG3_AT_76HZ,
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CG3_RDI
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};
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struct bt_regs {
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u32 addr;
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u32 color_map;
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u32 control;
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u32 cursor;
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};
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struct cg3_regs {
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struct bt_regs cmap;
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u8 control;
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u8 status;
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u8 cursor_start;
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u8 cursor_end;
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u8 h_blank_start;
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u8 h_blank_end;
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u8 h_sync_start;
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u8 h_sync_end;
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u8 comp_sync_end;
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u8 v_blank_start_high;
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u8 v_blank_start_low;
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u8 v_blank_end;
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u8 v_sync_start;
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u8 v_sync_end;
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u8 xfer_holdoff_start;
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u8 xfer_holdoff_end;
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};
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/* Offset of interesting structures in the OBIO space */
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#define CG3_REGS_OFFSET 0x400000UL
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#define CG3_RAM_OFFSET 0x800000UL
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struct cg3_par {
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spinlock_t lock;
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struct cg3_regs __iomem *regs;
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u32 sw_cmap[((256 * 3) + 3) / 4];
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u32 flags;
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#define CG3_FLAG_BLANKED 0x00000001
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#define CG3_FLAG_RDI 0x00000002
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unsigned long which_io;
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};
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/**
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* cg3_setcolreg - Optional function. Sets a color register.
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* @regno: boolean, 0 copy local, 1 get_user() function
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* @red: frame buffer colormap structure
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* @green: The green value which can be up to 16 bits wide
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* @blue: The blue value which can be up to 16 bits wide.
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* @transp: If supported the alpha value which can be up to 16 bits wide.
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* @info: frame buffer info structure
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*
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* The cg3 palette is loaded with 4 color values at each time
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* so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
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* We keep a sw copy of the hw cmap to assist us in this esoteric
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* loading procedure.
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*/
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static int cg3_setcolreg(unsigned regno,
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unsigned red, unsigned green, unsigned blue,
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unsigned transp, struct fb_info *info)
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{
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struct cg3_par *par = (struct cg3_par *) info->par;
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struct bt_regs __iomem *bt = &par->regs->cmap;
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unsigned long flags;
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u32 *p32;
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u8 *p8;
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int count;
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if (regno >= 256)
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return 1;
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red >>= 8;
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green >>= 8;
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blue >>= 8;
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spin_lock_irqsave(&par->lock, flags);
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p8 = (u8 *)par->sw_cmap + (regno * 3);
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p8[0] = red;
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p8[1] = green;
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p8[2] = blue;
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#define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */
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#define D4M4(x) ((x)&~0x3) /* (x/4)*4 */
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count = 3;
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p32 = &par->sw_cmap[D4M3(regno)];
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sbus_writel(D4M4(regno), &bt->addr);
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while (count--)
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sbus_writel(*p32++, &bt->color_map);
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#undef D4M3
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#undef D4M4
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spin_unlock_irqrestore(&par->lock, flags);
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return 0;
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}
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/**
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* cg3_blank - Optional function. Blanks the display.
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* @blank_mode: the blank mode we want.
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* @info: frame buffer structure that represents a single frame buffer
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*/
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static int cg3_blank(int blank, struct fb_info *info)
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{
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struct cg3_par *par = (struct cg3_par *) info->par;
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struct cg3_regs __iomem *regs = par->regs;
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unsigned long flags;
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u8 val;
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spin_lock_irqsave(&par->lock, flags);
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switch (blank) {
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case FB_BLANK_UNBLANK: /* Unblanking */
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val = sbus_readb(®s->control);
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val |= CG3_CR_ENABLE_VIDEO;
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sbus_writeb(val, ®s->control);
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par->flags &= ~CG3_FLAG_BLANKED;
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break;
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case FB_BLANK_NORMAL: /* Normal blanking */
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case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
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case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
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case FB_BLANK_POWERDOWN: /* Poweroff */
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val = sbus_readb(®s->control);
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val &= ~CG3_CR_ENABLE_VIDEO;
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sbus_writeb(val, ®s->control);
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par->flags |= CG3_FLAG_BLANKED;
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break;
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}
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spin_unlock_irqrestore(&par->lock, flags);
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return 0;
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}
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static struct sbus_mmap_map cg3_mmap_map[] = {
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{
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.voff = CG3_MMAP_OFFSET,
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.poff = CG3_RAM_OFFSET,
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.size = SBUS_MMAP_FBSIZE(1)
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},
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{ .size = 0 }
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};
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static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
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{
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struct cg3_par *par = (struct cg3_par *)info->par;
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return sbusfb_mmap_helper(cg3_mmap_map,
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info->fix.smem_start, info->fix.smem_len,
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par->which_io,
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vma);
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}
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static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
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{
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return sbusfb_ioctl_helper(cmd, arg, info,
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FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
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}
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/*
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* Initialisation
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*/
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static void cg3_init_fix(struct fb_info *info, int linebytes,
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struct device_node *dp)
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{
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strlcpy(info->fix.id, dp->name, sizeof(info->fix.id));
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info->fix.type = FB_TYPE_PACKED_PIXELS;
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info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
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info->fix.line_length = linebytes;
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info->fix.accel = FB_ACCEL_SUN_CGTHREE;
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}
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static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
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struct device_node *dp)
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{
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const char *params;
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char *p;
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int ww, hh;
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params = of_get_property(dp, "params", NULL);
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if (params) {
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ww = simple_strtoul(params, &p, 10);
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if (ww && *p == 'x') {
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hh = simple_strtoul(p + 1, &p, 10);
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if (hh && *p == '-') {
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if (var->xres != ww ||
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var->yres != hh) {
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var->xres = var->xres_virtual = ww;
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var->yres = var->yres_virtual = hh;
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}
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}
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}
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}
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}
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static u8 cg3regvals_66hz[] = { /* 1152 x 900, 66 Hz */
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0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
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0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
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0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
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0x10, 0x20, 0
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};
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static u8 cg3regvals_76hz[] = { /* 1152 x 900, 76 Hz */
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0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
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0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
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0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
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0x10, 0x24, 0
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};
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static u8 cg3regvals_rdi[] = { /* 640 x 480, cgRDI */
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0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
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0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
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0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
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0x10, 0x22, 0
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};
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static u8 *cg3_regvals[] = {
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cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
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};
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static u_char cg3_dacvals[] = {
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4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
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};
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static int cg3_do_default_mode(struct cg3_par *par)
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{
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enum cg3_type type;
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u8 *p;
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if (par->flags & CG3_FLAG_RDI)
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type = CG3_RDI;
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else {
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u8 status = sbus_readb(&par->regs->status), mon;
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if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
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mon = status & CG3_SR_RES_MASK;
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if (mon == CG3_SR_1152_900_76_A ||
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mon == CG3_SR_1152_900_76_B)
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type = CG3_AT_76HZ;
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else
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type = CG3_AT_66HZ;
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} else {
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printk(KERN_ERR "cgthree: can't handle SR %02x\n",
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status);
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return -EINVAL;
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}
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}
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for (p = cg3_regvals[type]; *p; p += 2) {
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u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
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sbus_writeb(p[1], regp);
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}
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for (p = cg3_dacvals; *p; p += 2) {
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u8 __iomem *regp;
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regp = (u8 __iomem *)&par->regs->cmap.addr;
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sbus_writeb(p[0], regp);
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regp = (u8 __iomem *)&par->regs->cmap.control;
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sbus_writeb(p[1], regp);
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}
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return 0;
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}
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static int cg3_probe(struct platform_device *op)
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{
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struct device_node *dp = op->dev.of_node;
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struct fb_info *info;
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struct cg3_par *par;
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int linebytes, err;
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info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);
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|
|
err = -ENOMEM;
|
||
|
|
if (!info)
|
||
|
|
goto out_err;
|
||
|
|
par = info->par;
|
||
|
|
|
||
|
|
spin_lock_init(&par->lock);
|
||
|
|
|
||
|
|
info->fix.smem_start = op->resource[0].start;
|
||
|
|
par->which_io = op->resource[0].flags & IORESOURCE_BITS;
|
||
|
|
|
||
|
|
sbusfb_fill_var(&info->var, dp, 8);
|
||
|
|
info->var.red.length = 8;
|
||
|
|
info->var.green.length = 8;
|
||
|
|
info->var.blue.length = 8;
|
||
|
|
if (!strcmp(dp->name, "cgRDI"))
|
||
|
|
par->flags |= CG3_FLAG_RDI;
|
||
|
|
if (par->flags & CG3_FLAG_RDI)
|
||
|
|
cg3_rdi_maybe_fixup_var(&info->var, dp);
|
||
|
|
|
||
|
|
linebytes = of_getintprop_default(dp, "linebytes",
|
||
|
|
info->var.xres);
|
||
|
|
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
|
||
|
|
|
||
|
|
par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
|
||
|
|
sizeof(struct cg3_regs), "cg3 regs");
|
||
|
|
if (!par->regs)
|
||
|
|
goto out_release_fb;
|
||
|
|
|
||
|
|
info->flags = FBINFO_DEFAULT;
|
||
|
|
info->fbops = &cg3_ops;
|
||
|
|
info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
|
||
|
|
info->fix.smem_len, "cg3 ram");
|
||
|
|
if (!info->screen_base)
|
||
|
|
goto out_unmap_regs;
|
||
|
|
|
||
|
|
cg3_blank(FB_BLANK_UNBLANK, info);
|
||
|
|
|
||
|
|
if (!of_find_property(dp, "width", NULL)) {
|
||
|
|
err = cg3_do_default_mode(par);
|
||
|
|
if (err)
|
||
|
|
goto out_unmap_screen;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = fb_alloc_cmap(&info->cmap, 256, 0);
|
||
|
|
if (err)
|
||
|
|
goto out_unmap_screen;
|
||
|
|
|
||
|
|
fb_set_cmap(&info->cmap, info);
|
||
|
|
|
||
|
|
cg3_init_fix(info, linebytes, dp);
|
||
|
|
|
||
|
|
err = register_framebuffer(info);
|
||
|
|
if (err < 0)
|
||
|
|
goto out_dealloc_cmap;
|
||
|
|
|
||
|
|
dev_set_drvdata(&op->dev, info);
|
||
|
|
|
||
|
|
printk(KERN_INFO "%pOF: cg3 at %lx:%lx\n",
|
||
|
|
dp, par->which_io, info->fix.smem_start);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
out_dealloc_cmap:
|
||
|
|
fb_dealloc_cmap(&info->cmap);
|
||
|
|
|
||
|
|
out_unmap_screen:
|
||
|
|
of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
|
||
|
|
|
||
|
|
out_unmap_regs:
|
||
|
|
of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
|
||
|
|
|
||
|
|
out_release_fb:
|
||
|
|
framebuffer_release(info);
|
||
|
|
|
||
|
|
out_err:
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int cg3_remove(struct platform_device *op)
|
||
|
|
{
|
||
|
|
struct fb_info *info = dev_get_drvdata(&op->dev);
|
||
|
|
struct cg3_par *par = info->par;
|
||
|
|
|
||
|
|
unregister_framebuffer(info);
|
||
|
|
fb_dealloc_cmap(&info->cmap);
|
||
|
|
|
||
|
|
of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
|
||
|
|
of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
|
||
|
|
|
||
|
|
framebuffer_release(info);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id cg3_match[] = {
|
||
|
|
{
|
||
|
|
.name = "cgthree",
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.name = "cgRDI",
|
||
|
|
},
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, cg3_match);
|
||
|
|
|
||
|
|
static struct platform_driver cg3_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "cg3",
|
||
|
|
.of_match_table = cg3_match,
|
||
|
|
},
|
||
|
|
.probe = cg3_probe,
|
||
|
|
.remove = cg3_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init cg3_init(void)
|
||
|
|
{
|
||
|
|
if (fb_get_options("cg3fb", NULL))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
return platform_driver_register(&cg3_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit cg3_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&cg3_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(cg3_init);
|
||
|
|
module_exit(cg3_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
|
||
|
|
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
|
||
|
|
MODULE_VERSION("2.0");
|
||
|
|
MODULE_LICENSE("GPL");
|