48 lines
1.4 KiB
Plaintext
48 lines
1.4 KiB
Plaintext
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* Renesas R8A7778 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7778. It includes two PLLs and
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several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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- compatible: Must be "renesas,r8a7778-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"plla", "pllb", "b", "out", "p", "s", and "s1".
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@ffc80000 {
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compatible = "renesas,r8a7778-cpg-clocks";
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reg = <0xffc80000 0x80>;
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#clock-cells = <1>;
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clocks = <&extal_clk>;
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clock-output-names = "plla", "pllb", "b",
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"out", "p", "s", "s1";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7778";
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reg = <0xffe4c000 0x100>;
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interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
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power-domains = <&cpg_clocks>;
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};
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