35 lines
1,011 B
Plaintext
35 lines
1,011 B
Plaintext
|
Device Tree Clock bindings for ZTE zx296702
|
||
|
|
|
||
|
|
This binding uses the common clock binding[1].
|
||
|
|
|
||
|
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible : shall be one of the following:
|
||
|
|
"zte,zx296702-topcrm-clk":
|
||
|
|
zx296702 top clock selection, divider and gating
|
||
|
|
|
||
|
|
"zte,zx296702-lsp0crpm-clk" and
|
||
|
|
"zte,zx296702-lsp1crpm-clk":
|
||
|
|
zx296702 device level clock selection and gating
|
||
|
|
|
||
|
|
- reg: Address and length of the register set
|
||
|
|
|
||
|
|
The clock consumer should specify the desired clock by having the clock
|
||
|
|
ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
|
||
|
|
for the full list of zx296702 clock IDs.
|
||
|
|
|
||
|
|
|
||
|
|
topclk: topcrm@09800000 {
|
||
|
|
compatible = "zte,zx296702-topcrm-clk";
|
||
|
|
reg = <0x09800000 0x1000>;
|
||
|
|
#clock-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0: serial@09405000 {
|
||
|
|
compatible = "zte,zx296702-uart";
|
||
|
|
reg = <0x09405000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&lsp1clk ZX296702_UART0_PCLK>;
|
||
|
|
};
|