50 lines
2.1 KiB
Plaintext
50 lines
2.1 KiB
Plaintext
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SMI (Smart Multimedia Interface) Common
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Mediatek SMI have two generations of HW architecture, here is the list
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which generation the SoCs use:
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generation 1: mt2701 and mt7623.
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generation 2: mt2712, mt6779, mt8173 and mt8183.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
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for generation 1, the register is at smi ao base(smi always on register
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base). Besides that, the smi async clock should be prepared and enabled for
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SMI generation 1 to transform the smi clock into emi clock domain, but that is
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not needed for SMI generation 2.
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Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-common"
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"mediatek,mt2712-smi-common"
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"mediatek,mt6779-smi-common"
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"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
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"mediatek,mt8173-smi-common"
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"mediatek,mt8183-smi-common"
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- reg : the register and size of the SMI block.
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- power-domains : a phandle to the power domain of this local arbiter.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
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for generation 2 smi HW as follows:
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- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
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the register.
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- "smi" : It's the clock for transfer data and command.
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They may be the same if both source clocks are the same.
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- "async" : asynchronous clock, it help transform the smi clock into the emi
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clock domain, this clock is only needed by generation 1 smi HW.
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and these 2 option clocks for generation 2 smi HW:
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- "gals0": the path0 clock of GALS(Global Async Local Sync).
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- "gals1": the path1 clock of GALS(Global Async Local Sync).
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Here is the list which has this GALS: mt6779 and mt8183.
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Example:
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smi_common: smi@14022000 {
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compatible = "mediatek,mt8173-smi-common";
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reg = <0 0x14022000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_SMI_COMMON>,
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<&mmsys CLK_MM_SMI_COMMON>;
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clock-names = "apb", "smi";
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};
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