184 lines
7.7 KiB
Plaintext
184 lines
7.7 KiB
Plaintext
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* Broadcom STB NAND Controller
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The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
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flash chips. It has a memory-mapped register interface for both control
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registers and for its data input/output buffer. On some SoCs, this controller is
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paired with a custom DMA engine (inventively named "Flash DMA") which supports
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basic PROGRAM and READ functions, among other features.
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This controller was originally designed for STB SoCs (BCM7xxx) but is now
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available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
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iProc/Cygnus. Its history includes several similar (but not fully register
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compatible) versions.
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Required properties:
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- compatible : May contain an SoC-specific compatibility string (see below)
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to account for any SoC-specific hardware bits that may be
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added on top of the base core controller.
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In addition, must contain compatibility information about
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the core NAND controller, of the following form:
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"brcm,brcmnand" and an appropriate version compatibility
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string, like "brcm,brcmnand-v7.0"
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Possible values:
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brcm,brcmnand-v4.0
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brcm,brcmnand-v5.0
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brcm,brcmnand-v6.0
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brcm,brcmnand-v6.1
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brcm,brcmnand-v6.2
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brcm,brcmnand-v7.0
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brcm,brcmnand-v7.1
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brcm,brcmnand-v7.2
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brcm,brcmnand
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- reg : the register start and length for NAND register region.
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(optional) Flash DMA register range (if present)
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(optional) NAND flash cache range (if at non-standard offset)
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- reg-names : a list of the names corresponding to the previous register
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ranges. Should contain "nand" and (optionally)
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"flash-dma" and/or "nand-cache".
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- interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
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FLASH_DMA_DONE
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- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done", if broken out as
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individual interrupts.
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May be "nand", if the SoC has the individual NAND
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interrupts multiplexed behind another custom piece of
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hardware
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- #address-cells : <1> - subnodes give the chip-select number
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- #size-cells : <0>
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Optional properties:
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- clock : reference to the clock for the NAND controller
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- clock-names : "nand" (required for the above clock)
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- brcm,nand-has-wp : Some versions of this IP include a write-protect
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(WP) control bit. It is always available on >=
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v7.0. Use this property to describe the rare
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earlier versions of this core that include WP
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-- Additional SoC-specific NAND controller properties --
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The NAND controller is integrated differently on the variety of SoCs on which it
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is found. Part of this integration involves providing status and enable bits
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with which to control the 8 exposed NAND interrupts, as well as hardware for
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configuring the endianness of the data bus. On some SoCs, these features are
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handled via standard, modular components (e.g., their interrupts look like a
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normal IRQ chip), but on others, they are controlled in unique and interesting
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ways, sometimes with registers that lump multiple NAND-related functions
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together. The former case can be described simply by the standard interrupts
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properties in the main controller node. But for the latter exceptional cases,
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we define additional 'compatible' properties and associated register resources within the NAND controller node above.
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- compatible: Can be one of several SoC-specific strings. Each SoC may have
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different requirements for its additional properties, as described below each
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bullet point below.
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* "brcm,nand-bcm63138"
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- reg: (required) the 'NAND_INT_BASE' register range, with separate status
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and enable registers
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- reg-names: (required) "nand-int-base"
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* "brcm,nand-bcm6368"
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- compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
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- reg: (required) the 'NAND_INTR_BASE' register range, with combined status
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and enable registers, and boot address registers
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- reg-names: (required) "nand-int-base"
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* "brcm,nand-iproc"
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- reg: (required) the "IDM" register range, for interrupt enable and APB
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bus access endianness configuration, and the "EXT" register range,
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for interrupt status/ack.
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- reg-names: (required) a list of the names corresponding to the previous
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register ranges. Should contain "iproc-idm" and "iproc-ext".
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* NAND chip-select
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Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes
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to represent enabled chip-selects which (may) contain NAND flash chips. Their
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properties are as follows.
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Required properties:
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- compatible : should contain "brcm,nandcs"
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- reg : a single integer representing the chip-select
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number (e.g., 0, 1, 2, etc.)
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- #address-cells : see partition.txt
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- #size-cells : see partition.txt
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- nand-ecc-strength : see nand.txt
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- nand-ecc-step-size : must be 512 or 1024. See nand.txt
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Optional properties:
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- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
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chip-select. See nand.txt
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- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
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expected for the ECC layout in use. This size, in
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addition to the strength and step-size,
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determines how the hardware BCH engine will lay
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out the parity bytes it stores on the flash.
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This property can be automatically determined by
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the flash geometry (particularly the NAND page
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and OOB size) in many cases, but when booting
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from NAND, the boot controller has only a limited
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number of available options for its default ECC
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layout.
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Each nandcs device node may optionally contain sub-nodes describing the flash
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partition mapping. See partition.txt for more detail.
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Example:
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nand@f0442800 {
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compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
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reg = <0xF0442800 0x600>,
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<0xF0443000 0x100>;
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reg-names = "nand", "flash-dma";
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interrupt-parent = <&hif_intr2_intc>;
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interrupts = <24>, <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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nandcs@1 {
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compatible = "brcm,nandcs";
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reg = <1>; // Chip select 1
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nand-on-flash-bbt;
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nand-ecc-strength = <12>;
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nand-ecc-step-size = <512>;
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// Partitions
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#address-cells = <1>; // <2>, for 64-bit offset
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#size-cells = <1>; // <2>, for 64-bit length
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flash0.rootfs@0 {
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reg = <0 0x10000000>;
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};
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flash0@0 {
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reg = <0 0>; // MTDPART_SIZ_FULL
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};
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flash0.kernel@10000000 {
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reg = <0x10000000 0x400000>;
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};
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};
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};
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nand@10000200 {
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compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
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"brcm,brcmnand-v4.0", "brcm,brcmnand";
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reg = <0x10000200 0x180>,
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<0x10000600 0x200>,
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<0x100000b0 0x10>;
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reg-names = "nand", "nand-cache", "nand-int-base";
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interrupt-parent = <&periph_intc>;
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interrupts = <50>;
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clocks = <&periph_clk 20>;
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clock-names = "nand";
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#address-cells = <1>;
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#size-cells = <0>;
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nand0: nandcs@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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nand-on-flash-bbt;
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nand-ecc-strength = <1>;
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nand-ecc-step-size = <512>;
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};
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};
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