74 lines
2.7 KiB
Plaintext
74 lines
2.7 KiB
Plaintext
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PHY nodes
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Required properties:
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- interrupts : interrupt specifier for the sole interrupt.
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- reg : The ID number for the phy, usually a small integer
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Optional Properties:
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- compatible: Compatible list, may contain
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"ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
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PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
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specifications. If neither of these are specified, the default is to
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assume clause 22.
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If the PHY reports an incorrect ID (or none at all) then the
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"compatible" list may contain an entry with the correct PHY ID in the
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form: "ethernet-phy-idAAAA.BBBB" where
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AAAA - The value of the 16 bit Phy Identifier 1 register as
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4 hex digits. This is the chip vendor OUI bits 3:18
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BBBB - The value of the 16 bit Phy Identifier 2 register as
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4 hex digits. This is the chip vendor OUI bits 19:24,
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followed by 10 bits of a vendor specific ID.
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The compatible list should not contain other values than those
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listed here.
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- max-speed: Maximum PHY supported speed (10, 100, 1000...)
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- broken-turn-around: If set, indicates the PHY device does not correctly
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release the turn around line low at the end of a MDIO transaction.
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- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
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compensate for the board being designed with the lanes swapped.
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- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
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TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
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bootstrap configuration caused by issues in PCB layout design.
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- eee-broken-100tx:
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- eee-broken-1000t:
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- eee-broken-10gt:
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- eee-broken-1000kx:
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- eee-broken-10gkx4:
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- eee-broken-10gkr:
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Mark the corresponding energy efficient ethernet mode as broken and
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request the ethernet to stop advertising it.
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- phy-is-integrated: If set, indicates that the PHY is integrated into the same
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physical package as the Ethernet MAC. If needed, muxers should be configured
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to ensure the integrated PHY is used. The absence of this property indicates
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the muxers should be configured so that the external PHY is used.
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- reset-gpios: The GPIO phandle and specifier for the PHY reset signal.
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- reset-assert-us: Delay after the reset was asserted in microseconds.
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If this property is missing the delay will be skipped.
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- reset-deassert-us: Delay after the reset was deasserted in microseconds.
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If this property is missing the delay will be skipped.
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Example:
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ethernet-phy@0 {
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compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
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interrupt-parent = <&PIC>;
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interrupts = <35 IRQ_TYPE_EDGE_RISING>;
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reg = <0>;
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reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <2000>;
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};
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