62 lines
2.1 KiB
Plaintext
62 lines
2.1 KiB
Plaintext
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STM32 Real Time Clock
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Required properties:
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- compatible: can be one of the following:
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- "st,stm32-rtc" for devices compatible with stm32(f4/f7).
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- "st,stm32h7-rtc" for devices compatible with stm32h7.
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- "st,stm32mp1-rtc" for devices compatible with stm32mp1.
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- reg: address range of rtc register set.
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- clocks: can use up to two clocks, depending on part used:
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- "rtc_ck": RTC clock source.
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- "pclk": RTC APB interface clock.
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It is not present on stm32(f4/f7).
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It is required on stm32(h7/mp1).
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- clock-names: must be "rtc_ck" and "pclk".
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It is required on stm32(h7/mp1).
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- interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required
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for rtc alarm wakeup interrupt.
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- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to
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access control register at offset, and change the dbp (Disable Backup
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Protection) bit represented by the mask, mandatory to disable/enable backup
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domain (RTC registers) write protection.
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It is required on stm32(f4/f7/h7).
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Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7):
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- assigned-clocks: reference to the rtc_ck clock entry.
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- assigned-clock-parents: phandle of the new parent clock of rtc_ck.
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Example:
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc 1 CLK_RTC>;
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assigned-clocks = <&rcc 1 CLK_RTC>;
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assigned-clock-parents = <&rcc 1 CLK_LSE>;
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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st,syscfg = <&pwrcfg 0x00 0x100>;
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};
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rtc: rtc@58004000 {
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compatible = "st,stm32h7-rtc";
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reg = <0x58004000 0x400>;
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clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
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clock-names = "pclk", "rtc_ck";
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assigned-clocks = <&rcc RTC_CK>;
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assigned-clock-parents = <&rcc LSE_CK>;
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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interrupt-names = "alarm";
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st,syscfg = <&pwrcfg 0x00 0x100>;
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};
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rtc: rtc@5c004000 {
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compatible = "st,stm32mp1-rtc";
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reg = <0x5c004000 0x400>;
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clocks = <&rcc RTCAPB>, <&rcc RTC>;
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clock-names = "pclk", "rtc_ck";
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interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>,
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<&exti 19 1>;
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};
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