29 lines
972 B
Plaintext
29 lines
972 B
Plaintext
|
NVIDIA Tegra30 timer
|
||
|
|
|
||
|
|
The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
|
||
|
|
running counter, and 5 watchdog modules. The first two channels may also
|
||
|
|
trigger a legacy watchdog reset.
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
|
||
|
|
- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
|
||
|
|
must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
|
||
|
|
<chip> is tegra124 or tegra132.
|
||
|
|
- reg : Specifies base physical address and size of the registers.
|
||
|
|
- interrupts : A list of 6 interrupts; one per each of timer channels 1
|
||
|
|
through 5, and one for the shared interrupt for the remaining channels.
|
||
|
|
- clocks : Must contain one entry, for the module clock.
|
||
|
|
See ../clocks/clock-bindings.txt for details.
|
||
|
|
|
||
|
|
timer {
|
||
|
|
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
|
||
|
|
reg = <0x60005000 0x400>;
|
||
|
|
interrupts = <0 0 0x04
|
||
|
|
0 1 0x04
|
||
|
|
0 41 0x04
|
||
|
|
0 42 0x04
|
||
|
|
0 121 0x04
|
||
|
|
0 122 0x04>;
|
||
|
|
clocks = <&tegra_car 214>;
|
||
|
|
};
|