57 lines
1.9 KiB
Plaintext
57 lines
1.9 KiB
Plaintext
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Rockchip SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"ref_clk" Controller reference clk, have to be 24 MHz
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"suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
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"bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
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operation and >= 30MHz for HS operation
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"grf_clk" Controller grf clk
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Phy documentation is provided in the following places:
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Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt - USB2.0 PHY
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Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt - Type-C PHY
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Example device nodes:
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usbdrd3_0: usb@fe800000 {
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compatible = "rockchip,rk3399-dwc3";
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clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
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<&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "grf_clk";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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usbdrd_dwc3_0: dwc3@fe800000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe800000 0x0 0x100000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "otg";
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};
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};
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usbdrd3_1: usb@fe900000 {
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compatible = "rockchip,rk3399-dwc3";
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clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
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<&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
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clock-names = "ref_clk", "suspend_clk",
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"bus_clk", "grf_clk";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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usbdrd_dwc3_1: dwc3@fe900000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe900000 0x0 0x100000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "otg";
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};
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};
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