609 lines
15 KiB
C
609 lines
15 KiB
C
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/*
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* iop13xx platform Initialization
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* Copyright (c) 2005-2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/dma-mapping.h>
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#include <linux/serial_8250.h>
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#include <linux/io.h>
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#include <linux/reboot.h>
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#ifdef CONFIG_MTD_PHYSMAP
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#include <linux/mtd/physmap.h>
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#endif
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/hardware/iop_adma.h>
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#include <mach/irqs.h>
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#define IOP13XX_UART_XTAL 33334000
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#define IOP13XX_SETUP_DEBUG 0
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#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
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/* Standard IO mapping for all IOP13XX based systems
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*/
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static struct map_desc iop13xx_std_desc[] __initdata = {
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{ /* mem mapped registers */
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.virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
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.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
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.length = IOP13XX_PMMR_SIZE,
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.type = MT_DEVICE,
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},
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};
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static struct resource iop13xx_uart0_resources[] = {
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[0] = {
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.start = IOP13XX_UART0_PHYS,
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.end = IOP13XX_UART0_PHYS + 0x3f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_UART0,
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.end = IRQ_IOP13XX_UART0,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_uart1_resources[] = {
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[0] = {
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.start = IOP13XX_UART1_PHYS,
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.end = IOP13XX_UART1_PHYS + 0x3f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_UART1,
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.end = IRQ_IOP13XX_UART1,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct plat_serial8250_port iop13xx_uart0_data[] = {
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{
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.membase = IOP13XX_UART0_VIRT,
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.mapbase = IOP13XX_UART0_PHYS,
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.irq = IRQ_IOP13XX_UART0,
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.uartclk = IOP13XX_UART_XTAL,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_SKIP_TEST,
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},
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{ },
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};
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static struct plat_serial8250_port iop13xx_uart1_data[] = {
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{
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.membase = IOP13XX_UART1_VIRT,
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.mapbase = IOP13XX_UART1_PHYS,
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.irq = IRQ_IOP13XX_UART1,
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.uartclk = IOP13XX_UART_XTAL,
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.regshift = 2,
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.iotype = UPIO_MEM,
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.flags = UPF_SKIP_TEST,
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},
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{ },
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};
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/* The ids are fixed up later in iop13xx_platform_init */
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static struct platform_device iop13xx_uart0 = {
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.name = "serial8250",
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.id = 0,
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.dev.platform_data = iop13xx_uart0_data,
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.num_resources = 2,
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.resource = iop13xx_uart0_resources,
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};
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static struct platform_device iop13xx_uart1 = {
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.name = "serial8250",
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.id = 0,
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.dev.platform_data = iop13xx_uart1_data,
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.num_resources = 2,
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.resource = iop13xx_uart1_resources
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};
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static struct resource iop13xx_i2c_0_resources[] = {
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[0] = {
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.start = IOP13XX_I2C0_PHYS,
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.end = IOP13XX_I2C0_PHYS + 0x18,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_I2C_0,
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.end = IRQ_IOP13XX_I2C_0,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_i2c_1_resources[] = {
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[0] = {
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.start = IOP13XX_I2C1_PHYS,
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.end = IOP13XX_I2C1_PHYS + 0x18,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_I2C_1,
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.end = IRQ_IOP13XX_I2C_1,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_i2c_2_resources[] = {
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[0] = {
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.start = IOP13XX_I2C2_PHYS,
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.end = IOP13XX_I2C2_PHYS + 0x18,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_I2C_2,
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.end = IRQ_IOP13XX_I2C_2,
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.flags = IORESOURCE_IRQ
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}
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};
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/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
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* we just use the same device name.
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*/
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/* The ids are fixed up later in iop13xx_platform_init */
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static struct platform_device iop13xx_i2c_0_controller = {
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.name = "IOP3xx-I2C",
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.id = 0,
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.num_resources = 2,
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.resource = iop13xx_i2c_0_resources
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};
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static struct platform_device iop13xx_i2c_1_controller = {
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.name = "IOP3xx-I2C",
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.id = 0,
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.num_resources = 2,
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.resource = iop13xx_i2c_1_resources
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};
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static struct platform_device iop13xx_i2c_2_controller = {
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.name = "IOP3xx-I2C",
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.id = 0,
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.num_resources = 2,
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.resource = iop13xx_i2c_2_resources
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};
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#ifdef CONFIG_MTD_PHYSMAP
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/* PBI Flash Device
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*/
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static struct physmap_flash_data iq8134x_flash_data = {
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.width = 2,
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};
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static struct resource iq8134x_flash_resource = {
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.start = IQ81340_FLASHBASE,
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.end = 0,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device iq8134x_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = { .platform_data = &iq8134x_flash_data, },
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.num_resources = 1,
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.resource = &iq8134x_flash_resource,
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};
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static unsigned long iq8134x_probe_flash_size(void)
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{
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uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
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int i;
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char query[3];
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unsigned long size = 0;
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int width = iq8134x_flash_data.width;
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if (flash_addr) {
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/* send CFI 'query' command */
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writew(0x98, flash_addr);
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/* check for CFI compliance */
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for (i = 0; i < 3 * width; i += width)
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query[i / width] = readb(flash_addr + (0x10 * width) + i);
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/* read the size */
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if (memcmp(query, "QRY", 3) == 0)
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size = 1 << readb(flash_addr + (0x27 * width));
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/* send CFI 'read array' command */
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writew(0xff, flash_addr);
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iounmap(flash_addr);
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}
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return size;
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}
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#endif
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/* ADMA Channels */
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static struct resource iop13xx_adma_0_resources[] = {
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[0] = {
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.start = IOP13XX_ADMA_PHYS_BASE(0),
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.end = IOP13XX_ADMA_UPPER_PA(0),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_ADMA0_EOT,
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.end = IRQ_IOP13XX_ADMA0_EOT,
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.flags = IORESOURCE_IRQ
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},
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[2] = {
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.start = IRQ_IOP13XX_ADMA0_EOC,
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.end = IRQ_IOP13XX_ADMA0_EOC,
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.flags = IORESOURCE_IRQ
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},
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[3] = {
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.start = IRQ_IOP13XX_ADMA0_ERR,
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.end = IRQ_IOP13XX_ADMA0_ERR,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_adma_1_resources[] = {
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[0] = {
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.start = IOP13XX_ADMA_PHYS_BASE(1),
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.end = IOP13XX_ADMA_UPPER_PA(1),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_ADMA1_EOT,
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.end = IRQ_IOP13XX_ADMA1_EOT,
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.flags = IORESOURCE_IRQ
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},
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[2] = {
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.start = IRQ_IOP13XX_ADMA1_EOC,
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.end = IRQ_IOP13XX_ADMA1_EOC,
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.flags = IORESOURCE_IRQ
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},
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[3] = {
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.start = IRQ_IOP13XX_ADMA1_ERR,
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.end = IRQ_IOP13XX_ADMA1_ERR,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct resource iop13xx_adma_2_resources[] = {
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[0] = {
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.start = IOP13XX_ADMA_PHYS_BASE(2),
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.end = IOP13XX_ADMA_UPPER_PA(2),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IOP13XX_ADMA2_EOT,
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.end = IRQ_IOP13XX_ADMA2_EOT,
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.flags = IORESOURCE_IRQ
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},
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[2] = {
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.start = IRQ_IOP13XX_ADMA2_EOC,
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.end = IRQ_IOP13XX_ADMA2_EOC,
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.flags = IORESOURCE_IRQ
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},
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[3] = {
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.start = IRQ_IOP13XX_ADMA2_ERR,
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.end = IRQ_IOP13XX_ADMA2_ERR,
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.flags = IORESOURCE_IRQ
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}
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};
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static u64 iop13xx_adma_dmamask = DMA_BIT_MASK(32);
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static struct iop_adma_platform_data iop13xx_adma_0_data = {
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.hw_id = 0,
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.pool_size = PAGE_SIZE,
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};
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static struct iop_adma_platform_data iop13xx_adma_1_data = {
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.hw_id = 1,
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.pool_size = PAGE_SIZE,
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};
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static struct iop_adma_platform_data iop13xx_adma_2_data = {
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.hw_id = 2,
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.pool_size = PAGE_SIZE,
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};
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/* The ids are fixed up later in iop13xx_platform_init */
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static struct platform_device iop13xx_adma_0_channel = {
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.name = "iop-adma",
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.id = 0,
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.num_resources = 4,
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.resource = iop13xx_adma_0_resources,
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.dev = {
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.dma_mask = &iop13xx_adma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = (void *) &iop13xx_adma_0_data,
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},
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};
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static struct platform_device iop13xx_adma_1_channel = {
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.name = "iop-adma",
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.id = 0,
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.num_resources = 4,
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.resource = iop13xx_adma_1_resources,
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.dev = {
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.dma_mask = &iop13xx_adma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = (void *) &iop13xx_adma_1_data,
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},
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};
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static struct platform_device iop13xx_adma_2_channel = {
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.name = "iop-adma",
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.id = 0,
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.num_resources = 4,
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.resource = iop13xx_adma_2_resources,
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.dev = {
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.dma_mask = &iop13xx_adma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = (void *) &iop13xx_adma_2_data,
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},
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};
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void __init iop13xx_map_io(void)
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{
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/* Initialize the Static Page Table maps */
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iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
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}
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|
|
static int init_uart;
|
||
|
|
static int init_i2c;
|
||
|
|
static int init_adma;
|
||
|
|
|
||
|
|
void __init iop13xx_platform_init(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
u32 uart_idx, i2c_idx, adma_idx, plat_idx;
|
||
|
|
struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
|
||
|
|
|
||
|
|
/* set the bases so we can read the device id */
|
||
|
|
iop13xx_set_atu_mmr_bases();
|
||
|
|
|
||
|
|
memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
|
||
|
|
|
||
|
|
if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
|
||
|
|
switch (iop13xx_dev_id()) {
|
||
|
|
/* enable both uarts on iop341 */
|
||
|
|
case 0x3380:
|
||
|
|
case 0x3384:
|
||
|
|
case 0x3388:
|
||
|
|
case 0x338c:
|
||
|
|
init_uart |= IOP13XX_INIT_UART_0;
|
||
|
|
init_uart |= IOP13XX_INIT_UART_1;
|
||
|
|
break;
|
||
|
|
/* only enable uart 1 */
|
||
|
|
default:
|
||
|
|
init_uart |= IOP13XX_INIT_UART_1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
|
||
|
|
switch (iop13xx_dev_id()) {
|
||
|
|
/* enable all i2c units on iop341 and iop342 */
|
||
|
|
case 0x3380:
|
||
|
|
case 0x3384:
|
||
|
|
case 0x3388:
|
||
|
|
case 0x338c:
|
||
|
|
case 0x3382:
|
||
|
|
case 0x3386:
|
||
|
|
case 0x338a:
|
||
|
|
case 0x338e:
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_0;
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_1;
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_2;
|
||
|
|
break;
|
||
|
|
/* only enable i2c 1 and 2 */
|
||
|
|
default:
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_1;
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_2;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (init_adma == IOP13XX_INIT_ADMA_DEFAULT) {
|
||
|
|
init_adma |= IOP13XX_INIT_ADMA_0;
|
||
|
|
init_adma |= IOP13XX_INIT_ADMA_1;
|
||
|
|
init_adma |= IOP13XX_INIT_ADMA_2;
|
||
|
|
}
|
||
|
|
|
||
|
|
plat_idx = 0;
|
||
|
|
uart_idx = 0;
|
||
|
|
i2c_idx = 0;
|
||
|
|
|
||
|
|
/* uart 1 (if enabled) is ttyS0 */
|
||
|
|
if (init_uart & IOP13XX_INIT_UART_1) {
|
||
|
|
PRINTK("Adding uart1 to platform device list\n");
|
||
|
|
iop13xx_uart1.id = uart_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] = &iop13xx_uart1;
|
||
|
|
}
|
||
|
|
if (init_uart & IOP13XX_INIT_UART_0) {
|
||
|
|
PRINTK("Adding uart0 to platform device list\n");
|
||
|
|
iop13xx_uart0.id = uart_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] = &iop13xx_uart0;
|
||
|
|
}
|
||
|
|
|
||
|
|
for(i = 0; i < IQ81340_NUM_I2C; i++) {
|
||
|
|
if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
|
||
|
|
printk("Adding i2c%d to platform device list\n", i);
|
||
|
|
switch(init_i2c & (1 << i)) {
|
||
|
|
case IOP13XX_INIT_I2C_0:
|
||
|
|
iop13xx_i2c_0_controller.id = i2c_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] =
|
||
|
|
&iop13xx_i2c_0_controller;
|
||
|
|
break;
|
||
|
|
case IOP13XX_INIT_I2C_1:
|
||
|
|
iop13xx_i2c_1_controller.id = i2c_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] =
|
||
|
|
&iop13xx_i2c_1_controller;
|
||
|
|
break;
|
||
|
|
case IOP13XX_INIT_I2C_2:
|
||
|
|
iop13xx_i2c_2_controller.id = i2c_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] =
|
||
|
|
&iop13xx_i2c_2_controller;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* initialize adma channel ids and capabilities */
|
||
|
|
adma_idx = 0;
|
||
|
|
for (i = 0; i < IQ81340_NUM_ADMA; i++) {
|
||
|
|
struct iop_adma_platform_data *plat_data;
|
||
|
|
if ((init_adma & (1 << i)) && IOP13XX_SETUP_DEBUG)
|
||
|
|
printk(KERN_INFO
|
||
|
|
"Adding adma%d to platform device list\n", i);
|
||
|
|
switch (init_adma & (1 << i)) {
|
||
|
|
case IOP13XX_INIT_ADMA_0:
|
||
|
|
iop13xx_adma_0_channel.id = adma_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] = &iop13xx_adma_0_channel;
|
||
|
|
plat_data = &iop13xx_adma_0_data;
|
||
|
|
dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_XOR, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
|
||
|
|
break;
|
||
|
|
case IOP13XX_INIT_ADMA_1:
|
||
|
|
iop13xx_adma_1_channel.id = adma_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] = &iop13xx_adma_1_channel;
|
||
|
|
plat_data = &iop13xx_adma_1_data;
|
||
|
|
dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_XOR, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
|
||
|
|
break;
|
||
|
|
case IOP13XX_INIT_ADMA_2:
|
||
|
|
iop13xx_adma_2_channel.id = adma_idx++;
|
||
|
|
iop13xx_devices[plat_idx++] = &iop13xx_adma_2_channel;
|
||
|
|
plat_data = &iop13xx_adma_2_data;
|
||
|
|
dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_XOR, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_PQ, plat_data->cap_mask);
|
||
|
|
dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_MTD_PHYSMAP
|
||
|
|
iq8134x_flash_resource.end = iq8134x_flash_resource.start +
|
||
|
|
iq8134x_probe_flash_size() - 1;
|
||
|
|
if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
|
||
|
|
iop13xx_devices[plat_idx++] = &iq8134x_flash;
|
||
|
|
else
|
||
|
|
printk(KERN_ERR "%s: Failed to probe flash size\n", __func__);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
platform_add_devices(iop13xx_devices, plat_idx);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init iop13xx_init_uart_setup(char *str)
|
||
|
|
{
|
||
|
|
if (str) {
|
||
|
|
while (*str != '\0') {
|
||
|
|
switch(*str) {
|
||
|
|
case '0':
|
||
|
|
init_uart |= IOP13XX_INIT_UART_0;
|
||
|
|
break;
|
||
|
|
case '1':
|
||
|
|
init_uart |= IOP13XX_INIT_UART_1;
|
||
|
|
break;
|
||
|
|
case ',':
|
||
|
|
case '=':
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
PRINTK("\"iop13xx_init_uart\" malformed"
|
||
|
|
" at character: \'%c\'", *str);
|
||
|
|
*(str + 1) = '\0';
|
||
|
|
init_uart = IOP13XX_INIT_UART_DEFAULT;
|
||
|
|
}
|
||
|
|
str++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init iop13xx_init_i2c_setup(char *str)
|
||
|
|
{
|
||
|
|
if (str) {
|
||
|
|
while (*str != '\0') {
|
||
|
|
switch(*str) {
|
||
|
|
case '0':
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_0;
|
||
|
|
break;
|
||
|
|
case '1':
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_1;
|
||
|
|
break;
|
||
|
|
case '2':
|
||
|
|
init_i2c |= IOP13XX_INIT_I2C_2;
|
||
|
|
break;
|
||
|
|
case ',':
|
||
|
|
case '=':
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
PRINTK("\"iop13xx_init_i2c\" malformed"
|
||
|
|
" at character: \'%c\'", *str);
|
||
|
|
*(str + 1) = '\0';
|
||
|
|
init_i2c = IOP13XX_INIT_I2C_DEFAULT;
|
||
|
|
}
|
||
|
|
str++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init iop13xx_init_adma_setup(char *str)
|
||
|
|
{
|
||
|
|
if (str) {
|
||
|
|
while (*str != '\0') {
|
||
|
|
switch (*str) {
|
||
|
|
case '0':
|
||
|
|
init_adma |= IOP13XX_INIT_ADMA_0;
|
||
|
|
break;
|
||
|
|
case '1':
|
||
|
|
init_adma |= IOP13XX_INIT_ADMA_1;
|
||
|
|
break;
|
||
|
|
case '2':
|
||
|
|
init_adma |= IOP13XX_INIT_ADMA_2;
|
||
|
|
break;
|
||
|
|
case ',':
|
||
|
|
case '=':
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
PRINTK("\"iop13xx_init_adma\" malformed"
|
||
|
|
" at character: \'%c\'", *str);
|
||
|
|
*(str + 1) = '\0';
|
||
|
|
init_adma = IOP13XX_INIT_ADMA_DEFAULT;
|
||
|
|
}
|
||
|
|
str++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
__setup("iop13xx_init_adma", iop13xx_init_adma_setup);
|
||
|
|
__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
|
||
|
|
__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
|
||
|
|
|
||
|
|
void iop13xx_restart(enum reboot_mode mode, const char *cmd)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* Reset the internal bus (warning both cores are reset)
|
||
|
|
*/
|
||
|
|
write_wdtcr(IOP_WDTCR_EN_ARM);
|
||
|
|
write_wdtcr(IOP_WDTCR_EN);
|
||
|
|
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
|
||
|
|
write_wdtcr(0x1000);
|
||
|
|
}
|