94 lines
3.2 KiB
C
94 lines
3.2 KiB
C
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/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PERF_EVENT_H
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#define __ASM_PERF_EVENT_H
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#include <asm/stack_pointer.h>
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#include <asm/ptrace.h>
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#define ARMV8_PMU_MAX_COUNTERS 32
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#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
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/*
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* Per-CPU PMCR: config reg
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*/
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#define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */
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#define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */
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#define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */
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#define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
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#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
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#define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */
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#define ARMV8_PMU_PMCR_N_MASK 0x1f
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#define ARMV8_PMU_PMCR_MASK 0x7f /* Mask for writable bits */
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/*
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* PMOVSR: counters overflow flag status reg
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*/
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#define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */
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#define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK
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/*
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* PMXEVTYPER: Event selection reg
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*/
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#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
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#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
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/*
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* PMUv3 event types: required events
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*/
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#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x00
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x03
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x04
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x10
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#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x11
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#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x12
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/*
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* Event filters for PMUv3
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*/
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#define ARMV8_PMU_EXCLUDE_EL1 (1 << 31)
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#define ARMV8_PMU_EXCLUDE_EL0 (1 << 30)
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#define ARMV8_PMU_INCLUDE_EL2 (1 << 27)
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/*
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* PMUSERENR: user enable reg
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*/
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#define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */
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#define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
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#define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
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#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
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#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
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#ifdef CONFIG_PERF_EVENTS
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struct pt_regs;
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
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extern unsigned long perf_misc_flags(struct pt_regs *regs);
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#define perf_misc_flags(regs) perf_misc_flags(regs)
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#define perf_arch_bpf_user_pt_regs(regs) ®s->user_regs
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#endif
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#define perf_arch_fetch_caller_regs(regs, __ip) { \
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(regs)->pc = (__ip); \
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(regs)->regs[29] = (unsigned long) __builtin_frame_address(0); \
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(regs)->sp = current_stack_pointer; \
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(regs)->pstate = PSR_MODE_EL1h; \
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}
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#endif
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