28 lines
967 B
C
28 lines
967 B
C
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||
|
#ifndef __ASM_MACH_JZ4740_BASE_H__
|
||
|
#define __ASM_MACH_JZ4740_BASE_H__
|
||
|
|
||
|
#define JZ4740_CPM_BASE_ADDR 0x10000000
|
||
|
#define JZ4740_INTC_BASE_ADDR 0x10001000
|
||
|
#define JZ4740_WDT_BASE_ADDR 0x10002000
|
||
|
#define JZ4740_TCU_BASE_ADDR 0x10002010
|
||
|
#define JZ4740_RTC_BASE_ADDR 0x10003000
|
||
|
#define JZ4740_GPIO_BASE_ADDR 0x10010000
|
||
|
#define JZ4740_AIC_BASE_ADDR 0x10020000
|
||
|
#define JZ4740_MSC_BASE_ADDR 0x10021000
|
||
|
#define JZ4740_UART0_BASE_ADDR 0x10030000
|
||
|
#define JZ4740_UART1_BASE_ADDR 0x10031000
|
||
|
#define JZ4740_I2C_BASE_ADDR 0x10042000
|
||
|
#define JZ4740_SSI_BASE_ADDR 0x10043000
|
||
|
#define JZ4740_SADC_BASE_ADDR 0x10070000
|
||
|
#define JZ4740_EMC_BASE_ADDR 0x13010000
|
||
|
#define JZ4740_DMAC_BASE_ADDR 0x13020000
|
||
|
#define JZ4740_UHC_BASE_ADDR 0x13030000
|
||
|
#define JZ4740_UDC_BASE_ADDR 0x13040000
|
||
|
#define JZ4740_LCD_BASE_ADDR 0x13050000
|
||
|
#define JZ4740_SLCD_BASE_ADDR 0x13050000
|
||
|
#define JZ4740_CIM_BASE_ADDR 0x13060000
|
||
|
#define JZ4740_IPU_BASE_ADDR 0x13080000
|
||
|
|
||
|
#endif
|