70 lines
2.7 KiB
Plaintext
70 lines
2.7 KiB
Plaintext
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/*
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* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
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*
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* Copyright 2014 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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clockgen: global-utilities@e1000 {
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compatible = "fsl,qoriq-clockgen-2.0";
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ranges = <0x0 0xe1000 0x1000>;
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reg = <0xe1000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <2>;
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sysclk: sysclk {
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#clock-cells = <0>;
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compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
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clock-output-names = "sysclk";
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};
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pll0: pll0@800 {
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#clock-cells = <1>;
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reg = <0x800 0x4>;
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compatible = "fsl,qoriq-core-pll-2.0";
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clocks = <&sysclk>;
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clock-output-names = "pll0", "pll0-div2", "pll0-div4";
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};
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pll1: pll1@820 {
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#clock-cells = <1>;
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reg = <0x820 0x4>;
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compatible = "fsl,qoriq-core-pll-2.0";
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clocks = <&sysclk>;
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clock-output-names = "pll1", "pll1-div2", "pll1-div4";
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};
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platform_pll: platform-pll@c00 {
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#clock-cells = <1>;
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reg = <0xc00 0x4>;
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compatible = "fsl,qoriq-platform-pll-2.0";
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clocks = <&sysclk>;
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clock-output-names = "platform-pll", "platform-pll-div2";
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};
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};
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