472 lines
11 KiB
ArmAsm
472 lines
11 KiB
ArmAsm
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/*
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L2CR functions
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Copyright © 1997-1998 by PowerLogix R & D, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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Thur, Dec. 12, 1998.
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- First public release, contributed by PowerLogix.
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***********
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Sat, Aug. 7, 1999.
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- Terry: Made sure code disabled interrupts before running. (Previously
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it was assumed interrupts were already disabled).
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- Terry: Updated for tentative G4 support. 4MB of memory is now flushed
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instead of 2MB. (Prob. only 3 is necessary).
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- Terry: Updated for workaround to HID0[DPM] processor bug
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during global invalidates.
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***********
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Thu, July 13, 2000.
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- Terry: Added isync to correct for an errata.
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22 August 2001.
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- DanM: Finally added the 7450 patch I've had for the past
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several months. The L2CR is similar, but I'm going
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to assume the user of this functions knows what they
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are doing.
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Author: Terry Greeniaus (tgree@phys.ualberta.ca)
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Please e-mail updates to this file to me, thanks!
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*/
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/feature-fixups.h>
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/* Usage:
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When setting the L2CR register, you must do a few special
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things. If you are enabling the cache, you must perform a
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global invalidate. If you are disabling the cache, you must
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flush the cache contents first. This routine takes care of
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doing these things. When first enabling the cache, make sure
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you pass in the L2CR you want, as well as passing in the
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global invalidate bit set. A global invalidate will only be
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performed if the L2I bit is set in applyThis. When enabling
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the cache, you should also set the L2E bit in applyThis. If
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you want to modify the L2CR contents after the cache has been
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enabled, the recommended procedure is to first call
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__setL2CR(0) to disable the cache and then call it again with
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the new values for L2CR. Examples:
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_setL2CR(0) - disables the cache
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_setL2CR(0xB3A04000) - enables my G3 upgrade card:
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- L2E set to turn on the cache
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- L2SIZ set to 1MB
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- L2CLK set to 1:1
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- L2RAM set to pipelined synchronous late-write
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- L2I set to perform a global invalidation
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- L2OH set to 0.5 nS
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- L2DF set because this upgrade card
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requires it
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A similar call should work for your card. You need to know
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the correct setting for your card and then place them in the
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fields I have outlined above. Other fields support optional
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features, such as L2DO which caches only data, or L2TS which
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causes cache pushes from the L1 cache to go to the L2 cache
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instead of to main memory.
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IMPORTANT:
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Starting with the 7450, the bits in this register have moved
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or behave differently. The Enable, Parity Enable, Size,
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and L2 Invalidate are the only bits that have not moved.
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The size is read-only for these processors with internal L2
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cache, and the invalidate is a control as well as status.
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-- Dan
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*/
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/*
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* Summary: this procedure ignores the L2I bit in the value passed in,
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* flushes the cache if it was already enabled, always invalidates the
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* cache, then enables the cache if the L2E bit is set in the value
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* passed in.
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* -- paulus.
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*/
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_GLOBAL(_set_L2CR)
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/* Make sure this is a 750 or 7400 chip */
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BEGIN_FTR_SECTION
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li r3,-1
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blr
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END_FTR_SECTION_IFCLR(CPU_FTR_L2CR)
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mflr r9
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/* Stop DST streams */
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BEGIN_FTR_SECTION
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DSSALL
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sync
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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/* Turn off interrupts and data relocation. */
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mfmsr r7 /* Save MSR in r7 */
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rlwinm r4,r7,0,17,15
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rlwinm r4,r4,0,28,26 /* Turn off DR bit */
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sync
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mtmsr r4
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isync
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/* Before we perform the global invalidation, we must disable dynamic
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* power management via HID0[DPM] to work around a processor bug where
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* DPM can possibly interfere with the state machine in the processor
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* that invalidates the L2 cache tags.
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*/
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mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
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rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
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sync
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mtspr SPRN_HID0,r4 /* Disable DPM */
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sync
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/* Get the current enable bit of the L2CR into r4 */
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mfspr r4,SPRN_L2CR
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/* Tweak some bits */
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rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
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rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
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rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
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/* Check to see if we need to flush */
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rlwinm. r4,r4,0,0,0
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beq 2f
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/* Flush the cache. First, read the first 4MB of memory (physical) to
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* put new data in the cache. (Actually we only need
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* the size of the L2 cache plus the size of the L1 cache, but 4MB will
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* cover everything just to be safe).
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*/
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/**** Might be a good idea to set L2DO here - to prevent instructions
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from getting into the cache. But since we invalidate
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the next time we enable the cache it doesn't really matter.
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Don't do this unless you accommodate all processor variations.
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The bit moved on the 7450.....
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****/
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BEGIN_FTR_SECTION
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/* Disable L2 prefetch on some 745x and try to ensure
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* L2 prefetch engines are idle. As explained by errata
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* text, we can't be sure they are, we just hope very hard
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* that well be enough (sic !). At least I noticed Apple
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* doesn't even bother doing the dcbf's here...
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*/
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mfspr r4,SPRN_MSSCR0
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rlwinm r4,r4,0,0,29
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sync
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mtspr SPRN_MSSCR0,r4
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sync
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isync
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lis r4,KERNELBASE@h
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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dcbf 0,r4
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END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
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/* TODO: use HW flush assist when available */
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lis r4,0x0002
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mtctr r4
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li r4,0
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1:
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lwzx r0,0,r4
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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isync
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/* Now, flush the first 4MB of memory */
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lis r4,0x0002
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mtctr r4
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li r4,0
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sync
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1:
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dcbf 0,r4
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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2:
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/* Set up the L2CR configuration bits (and switch L2 off) */
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/* CPU errata: Make sure the mtspr below is already in the
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* L1 icache
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*/
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b 20f
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.balign L1_CACHE_BYTES
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22:
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sync
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mtspr SPRN_L2CR,r3
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sync
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b 23f
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20:
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b 21f
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21: sync
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isync
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b 22b
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23:
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/* Perform a global invalidation */
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oris r3,r3,0x0020
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sync
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mtspr SPRN_L2CR,r3
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sync
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isync /* For errata */
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BEGIN_FTR_SECTION
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/* On the 7450, we wait for the L2I bit to clear......
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*/
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10: mfspr r3,SPRN_L2CR
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andis. r4,r3,0x0020
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bne 10b
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b 11f
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END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
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/* Wait for the invalidation to complete */
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3: mfspr r3,SPRN_L2CR
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rlwinm. r4,r3,0,31,31
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bne 3b
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11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
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sync
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mtspr SPRN_L2CR,r3
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sync
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/* See if we need to enable the cache */
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cmplwi r5,0
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beq 4f
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/* Enable the cache */
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oris r3,r3,0x8000
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mtspr SPRN_L2CR,r3
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sync
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/* Enable L2 HW prefetch on 744x/745x */
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BEGIN_FTR_SECTION
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mfspr r3,SPRN_MSSCR0
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ori r3,r3,3
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sync
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mtspr SPRN_MSSCR0,r3
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sync
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isync
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END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
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4:
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/* Restore HID0[DPM] to whatever it was before */
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sync
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mtspr 1008,r8
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sync
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/* Restore MSR (restores EE and DR bits to original state) */
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SYNC
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mtmsr r7
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isync
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mtlr r9
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blr
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_GLOBAL(_get_L2CR)
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/* Return the L2CR contents */
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li r3,0
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BEGIN_FTR_SECTION
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mfspr r3,SPRN_L2CR
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END_FTR_SECTION_IFSET(CPU_FTR_L2CR)
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blr
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/*
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* Here is a similar routine for dealing with the L3 cache
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* on the 745x family of chips
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*/
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_GLOBAL(_set_L3CR)
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/* Make sure this is a 745x chip */
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BEGIN_FTR_SECTION
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li r3,-1
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blr
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END_FTR_SECTION_IFCLR(CPU_FTR_L3CR)
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/* Turn off interrupts and data relocation. */
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mfmsr r7 /* Save MSR in r7 */
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rlwinm r4,r7,0,17,15
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rlwinm r4,r4,0,28,26 /* Turn off DR bit */
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sync
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mtmsr r4
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isync
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/* Stop DST streams */
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DSSALL
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sync
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/* Get the current enable bit of the L3CR into r4 */
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mfspr r4,SPRN_L3CR
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/* Tweak some bits */
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rlwinm r5,r3,0,0,0 /* r5 contains the new enable bit */
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rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
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rlwinm r3,r3,0,2,31 /* Turn off the enable & PE bits */
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rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
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/* Check to see if we need to flush */
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rlwinm. r4,r4,0,0,0
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beq 2f
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/* Flush the cache.
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*/
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/* TODO: use HW flush assist */
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lis r4,0x0008
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mtctr r4
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li r4,0
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1:
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lwzx r0,0,r4
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dcbf 0,r4
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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2:
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/* Set up the L3CR configuration bits (and switch L3 off) */
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sync
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mtspr SPRN_L3CR,r3
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sync
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oris r3,r3,L3CR_L3RES@h /* Set reserved bit 5 */
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mtspr SPRN_L3CR,r3
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sync
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oris r3,r3,L3CR_L3CLKEN@h /* Set clken */
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mtspr SPRN_L3CR,r3
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sync
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/* Wait for stabilize */
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li r0,256
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mtctr r0
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1: bdnz 1b
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/* Perform a global invalidation */
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ori r3,r3,0x0400
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sync
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mtspr SPRN_L3CR,r3
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sync
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isync
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/* We wait for the L3I bit to clear...... */
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10: mfspr r3,SPRN_L3CR
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andi. r4,r3,0x0400
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bne 10b
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/* Clear CLKEN */
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rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
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mtspr SPRN_L3CR,r3
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sync
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/* Wait for stabilize */
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li r0,256
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mtctr r0
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1: bdnz 1b
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/* See if we need to enable the cache */
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cmplwi r5,0
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beq 4f
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|
/* Enable the cache */
|
||
|
|
oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
|
||
|
|
mtspr SPRN_L3CR,r3
|
||
|
|
sync
|
||
|
|
|
||
|
|
/* Wait for stabilize */
|
||
|
|
li r0,256
|
||
|
|
mtctr r0
|
||
|
|
1: bdnz 1b
|
||
|
|
|
||
|
|
/* Restore MSR (restores EE and DR bits to original state) */
|
||
|
|
4: SYNC
|
||
|
|
mtmsr r7
|
||
|
|
isync
|
||
|
|
blr
|
||
|
|
|
||
|
|
_GLOBAL(_get_L3CR)
|
||
|
|
/* Return the L3CR contents */
|
||
|
|
li r3,0
|
||
|
|
BEGIN_FTR_SECTION
|
||
|
|
mfspr r3,SPRN_L3CR
|
||
|
|
END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
|
||
|
|
blr
|
||
|
|
|
||
|
|
/* --- End of PowerLogix code ---
|
||
|
|
*/
|
||
|
|
|
||
|
|
|
||
|
|
/* flush_disable_L1() - Flush and disable L1 cache
|
||
|
|
*
|
||
|
|
* clobbers r0, r3, ctr, cr0
|
||
|
|
* Must be called with interrupts disabled and MMU enabled.
|
||
|
|
*/
|
||
|
|
_GLOBAL(__flush_disable_L1)
|
||
|
|
/* Stop pending alitvec streams and memory accesses */
|
||
|
|
BEGIN_FTR_SECTION
|
||
|
|
DSSALL
|
||
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||
|
|
sync
|
||
|
|
|
||
|
|
/* Load counter to 0x4000 cache lines (512k) and
|
||
|
|
* load cache with datas
|
||
|
|
*/
|
||
|
|
li r3,0x4000 /* 512kB / 32B */
|
||
|
|
mtctr r3
|
||
|
|
lis r3,KERNELBASE@h
|
||
|
|
1:
|
||
|
|
lwz r0,0(r3)
|
||
|
|
addi r3,r3,0x0020 /* Go to start of next cache line */
|
||
|
|
bdnz 1b
|
||
|
|
isync
|
||
|
|
sync
|
||
|
|
|
||
|
|
/* Now flush those cache lines */
|
||
|
|
li r3,0x4000 /* 512kB / 32B */
|
||
|
|
mtctr r3
|
||
|
|
lis r3,KERNELBASE@h
|
||
|
|
1:
|
||
|
|
dcbf 0,r3
|
||
|
|
addi r3,r3,0x0020 /* Go to start of next cache line */
|
||
|
|
bdnz 1b
|
||
|
|
sync
|
||
|
|
|
||
|
|
/* We can now disable the L1 cache (HID0:DCE, HID0:ICE) */
|
||
|
|
mfspr r3,SPRN_HID0
|
||
|
|
rlwinm r3,r3,0,18,15
|
||
|
|
mtspr SPRN_HID0,r3
|
||
|
|
sync
|
||
|
|
isync
|
||
|
|
blr
|
||
|
|
|
||
|
|
/* inval_enable_L1 - Invalidate and enable L1 cache
|
||
|
|
*
|
||
|
|
* Assumes L1 is already disabled and MSR:EE is off
|
||
|
|
*
|
||
|
|
* clobbers r3
|
||
|
|
*/
|
||
|
|
_GLOBAL(__inval_enable_L1)
|
||
|
|
/* Enable and then Flash inval the instruction & data cache */
|
||
|
|
mfspr r3,SPRN_HID0
|
||
|
|
ori r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI
|
||
|
|
sync
|
||
|
|
isync
|
||
|
|
mtspr SPRN_HID0,r3
|
||
|
|
xori r3,r3, HID0_ICFI|HID0_DCI
|
||
|
|
mtspr SPRN_HID0,r3
|
||
|
|
sync
|
||
|
|
|
||
|
|
blr
|
||
|
|
|
||
|
|
|