572 lines
14 KiB
C
572 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas - AP-325RXA
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* (Compatible with Algo System ., LTD. - AP-320A)
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Author : Yusuke Goda <goda.yuske@renesas.com>
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*/
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#include <asm/clock.h>
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#include <asm/io.h>
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#include <asm/suspend.h>
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#include <cpu/sh7723.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <linux/gpio/machine.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/memblock.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/host.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/sh_flctl.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <linux/sh_intc.h>
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#include <linux/smsc911x.h>
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#include <linux/videodev2.h>
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#include <media/drv-intf/renesas-ceu.h>
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#include <media/i2c/ov772x.h>
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#include <video/sh_mobile_lcdc.h>
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#define CEU_BUFFER_MEMORY_SIZE (4 << 20)
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static phys_addr_t ceu_dma_membase;
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/* Dummy supplies, where voltage doesn't matter */
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static struct regulator_consumer_supply dummy_supplies[] = {
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REGULATOR_SUPPLY("vddvario", "smsc911x"),
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REGULATOR_SUPPLY("vdd33a", "smsc911x"),
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};
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static struct smsc911x_platform_config smsc911x_config = {
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.phy_interface = PHY_INTERFACE_MODE_MII,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
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.flags = SMSC911X_USE_32BIT,
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};
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static struct resource smsc9118_resources[] = {
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[0] = {
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.start = 0xb6080000,
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.end = 0xb60fffff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x660),
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.end = evt2irq(0x660),
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device smsc9118_device = {
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.name = "smsc911x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smsc9118_resources),
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.resource = smsc9118_resources,
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.dev = {
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.platform_data = &smsc911x_config,
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},
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};
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/*
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* AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
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* If this area erased, this board can not boot.
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*/
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static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
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{
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.name = "uboot",
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.offset = 0,
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.size = (1 * 1024 * 1024),
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.mask_flags = MTD_WRITEABLE, /* Read-only */
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}, {
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = (2 * 1024 * 1024),
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}, {
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.name = "free-area0",
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.offset = MTDPART_OFS_APPEND,
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.size = ((7 * 1024 * 1024) + (512 * 1024)),
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}, {
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.name = "CPLD-Data",
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.offset = MTDPART_OFS_APPEND,
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.mask_flags = MTD_WRITEABLE, /* Read-only */
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.size = (1024 * 128 * 2),
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}, {
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.name = "free-area1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct physmap_flash_data ap325rxa_nor_flash_data = {
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.width = 2,
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.parts = ap325rxa_nor_flash_partitions,
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.nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
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};
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static struct resource ap325rxa_nor_flash_resources[] = {
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[0] = {
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.name = "NOR Flash",
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.start = 0x00000000,
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.end = 0x00ffffff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device ap325rxa_nor_flash_device = {
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.name = "physmap-flash",
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.resource = ap325rxa_nor_flash_resources,
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.num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
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.dev = {
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.platform_data = &ap325rxa_nor_flash_data,
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},
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};
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static struct mtd_partition nand_partition_info[] = {
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{
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.name = "nand_data",
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.offset = 0,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct resource nand_flash_resources[] = {
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[0] = {
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.start = 0xa4530000,
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.end = 0xa45300ff,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct sh_flctl_platform_data nand_flash_data = {
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.parts = nand_partition_info,
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.nr_parts = ARRAY_SIZE(nand_partition_info),
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.flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
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.has_hwecc = 1,
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};
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static struct platform_device nand_flash_device = {
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.name = "sh_flctl",
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.resource = nand_flash_resources,
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.num_resources = ARRAY_SIZE(nand_flash_resources),
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.dev = {
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.platform_data = &nand_flash_data,
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},
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};
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#define FPGA_LCDREG 0xB4100180
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#define FPGA_BKLREG 0xB4100212
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#define FPGA_LCDREG_VAL 0x0018
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#define PORT_MSELCRB 0xA4050182
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#define PORT_HIZCRC 0xA405015C
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#define PORT_DRVCRA 0xA405018A
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#define PORT_DRVCRB 0xA405018C
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static int ap320_wvga_set_brightness(int brightness)
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{
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if (brightness) {
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gpio_set_value(GPIO_PTS3, 0);
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__raw_writew(0x100, FPGA_BKLREG);
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} else {
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__raw_writew(0, FPGA_BKLREG);
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gpio_set_value(GPIO_PTS3, 1);
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}
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return 0;
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}
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static void ap320_wvga_power_on(void)
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{
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msleep(100);
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/* ASD AP-320/325 LCD ON */
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__raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
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}
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static void ap320_wvga_power_off(void)
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{
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/* ASD AP-320/325 LCD OFF */
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__raw_writew(0, FPGA_LCDREG);
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}
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static const struct fb_videomode ap325rxa_lcdc_modes[] = {
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{
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.name = "LB070WV1",
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.xres = 800,
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.yres = 480,
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.left_margin = 32,
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.right_margin = 160,
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.hsync_len = 8,
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.upper_margin = 63,
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.lower_margin = 80,
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.vsync_len = 1,
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.sync = 0, /* hsync and vsync are active low */
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},
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};
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static struct sh_mobile_lcdc_info lcdc_info = {
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.clock_source = LCDC_CLK_EXTERNAL,
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.ch[0] = {
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.chan = LCDC_CHAN_MAINLCD,
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.fourcc = V4L2_PIX_FMT_RGB565,
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.interface_type = RGB18,
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.clock_divider = 1,
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.lcd_modes = ap325rxa_lcdc_modes,
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.num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
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.panel_cfg = {
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.width = 152, /* 7.0 inch */
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.height = 91,
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.display_on = ap320_wvga_power_on,
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.display_off = ap320_wvga_power_off,
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},
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.bl_info = {
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.name = "sh_mobile_lcdc_bl",
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.max_brightness = 1,
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.set_brightness = ap320_wvga_set_brightness,
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},
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}
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};
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static struct resource lcdc_resources[] = {
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[0] = {
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.name = "LCDC",
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.start = 0xfe940000, /* P4-only space */
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.end = 0xfe942fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x580),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device lcdc_device = {
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.name = "sh_mobile_lcdc_fb",
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.num_resources = ARRAY_SIZE(lcdc_resources),
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.resource = lcdc_resources,
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.dev = {
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.platform_data = &lcdc_info,
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},
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};
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/* Powerdown/reset gpios for CEU image sensors */
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static struct gpiod_lookup_table ov7725_gpios = {
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.dev_id = "0-0021",
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.table = {
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GPIO_LOOKUP("sh7723_pfc", GPIO_PTZ5, "reset", GPIO_ACTIVE_LOW),
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},
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};
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static struct ceu_platform_data ceu0_pdata = {
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.num_subdevs = 1,
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.subdevs = {
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{ /* [0] = ov7725 */
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.flags = 0,
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.bus_width = 8,
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.bus_shift = 0,
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.i2c_adapter_id = 0,
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.i2c_address = 0x21,
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},
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},
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};
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static struct resource ceu_resources[] = {
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[0] = {
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.name = "CEU",
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.start = 0xfe910000,
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.end = 0xfe91009f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x880),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ap325rxa_ceu_device = {
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.name = "renesas-ceu",
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.id = 0, /* "ceu.0" clock */
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.num_resources = ARRAY_SIZE(ceu_resources),
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.resource = ceu_resources,
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.dev = {
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.platform_data = &ceu0_pdata,
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},
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};
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/* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
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static struct regulator_consumer_supply fixed3v3_power_consumers[] =
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{
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REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
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REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
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REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
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REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
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};
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static struct resource sdhi0_cn3_resources[] = {
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[0] = {
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.name = "SDHI0",
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.start = 0x04ce0000,
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.end = 0x04ce00ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0xe80),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct tmio_mmc_data sdhi0_cn3_data = {
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.capabilities = MMC_CAP_SDIO_IRQ,
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};
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static struct platform_device sdhi0_cn3_device = {
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.name = "sh_mobile_sdhi",
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.id = 0, /* "sdhi0" clock */
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.num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
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.resource = sdhi0_cn3_resources,
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.dev = {
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.platform_data = &sdhi0_cn3_data,
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},
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};
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static struct resource sdhi1_cn7_resources[] = {
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[0] = {
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.name = "SDHI1",
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.start = 0x04cf0000,
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.end = 0x04cf00ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x4e0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct tmio_mmc_data sdhi1_cn7_data = {
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.capabilities = MMC_CAP_SDIO_IRQ,
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};
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static struct platform_device sdhi1_cn7_device = {
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.name = "sh_mobile_sdhi",
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.id = 1, /* "sdhi1" clock */
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.num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
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.resource = sdhi1_cn7_resources,
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.dev = {
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.platform_data = &sdhi1_cn7_data,
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},
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};
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static struct ov772x_camera_info ov7725_info = {
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|
.flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
|
||
|
|
.edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct i2c_board_info ap325rxa_i2c_devices[] __initdata = {
|
||
|
|
{
|
||
|
|
I2C_BOARD_INFO("pcf8563", 0x51),
|
||
|
|
},
|
||
|
|
{
|
||
|
|
I2C_BOARD_INFO("ov772x", 0x21),
|
||
|
|
.platform_data = &ov7725_info,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device *ap325rxa_devices[] __initdata = {
|
||
|
|
&smsc9118_device,
|
||
|
|
&ap325rxa_nor_flash_device,
|
||
|
|
&lcdc_device,
|
||
|
|
&nand_flash_device,
|
||
|
|
&sdhi0_cn3_device,
|
||
|
|
&sdhi1_cn7_device,
|
||
|
|
};
|
||
|
|
|
||
|
|
extern char ap325rxa_sdram_enter_start;
|
||
|
|
extern char ap325rxa_sdram_enter_end;
|
||
|
|
extern char ap325rxa_sdram_leave_start;
|
||
|
|
extern char ap325rxa_sdram_leave_end;
|
||
|
|
|
||
|
|
static int __init ap325rxa_devices_setup(void)
|
||
|
|
{
|
||
|
|
/* register board specific self-refresh code */
|
||
|
|
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
|
||
|
|
&ap325rxa_sdram_enter_start,
|
||
|
|
&ap325rxa_sdram_enter_end,
|
||
|
|
&ap325rxa_sdram_leave_start,
|
||
|
|
&ap325rxa_sdram_leave_end);
|
||
|
|
|
||
|
|
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
|
||
|
|
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
|
||
|
|
regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||
|
|
|
||
|
|
/* LD3 and LD4 LEDs */
|
||
|
|
gpio_request(GPIO_PTX5, NULL); /* RUN */
|
||
|
|
gpio_direction_output(GPIO_PTX5, 1);
|
||
|
|
gpio_export(GPIO_PTX5, 0);
|
||
|
|
|
||
|
|
gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
|
||
|
|
gpio_direction_output(GPIO_PTX4, 0);
|
||
|
|
gpio_export(GPIO_PTX4, 0);
|
||
|
|
|
||
|
|
/* SW1 input */
|
||
|
|
gpio_request(GPIO_PTF7, NULL); /* MODE */
|
||
|
|
gpio_direction_input(GPIO_PTF7);
|
||
|
|
gpio_export(GPIO_PTF7, 0);
|
||
|
|
|
||
|
|
/* LCDC */
|
||
|
|
gpio_request(GPIO_FN_LCDD15, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD14, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD13, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD12, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD11, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD10, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD9, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD8, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD7, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD6, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD5, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD4, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD3, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD2, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD1, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDD0, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDDCK, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDVEPWC, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDVCPWC, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDVSYN, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDHSYN, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDDISP, NULL);
|
||
|
|
gpio_request(GPIO_FN_LCDDON, NULL);
|
||
|
|
|
||
|
|
/* LCD backlight */
|
||
|
|
gpio_request(GPIO_PTS3, NULL);
|
||
|
|
gpio_direction_output(GPIO_PTS3, 1);
|
||
|
|
|
||
|
|
/* CEU */
|
||
|
|
gpio_request(GPIO_FN_VIO_CLK2, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_VD2, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_HD2, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_FLD, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_CKO, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D15, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D14, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D13, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D12, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D11, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D10, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D9, NULL);
|
||
|
|
gpio_request(GPIO_FN_VIO_D8, NULL);
|
||
|
|
|
||
|
|
gpio_request(GPIO_PTZ7, NULL);
|
||
|
|
gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
|
||
|
|
gpio_request(GPIO_PTZ6, NULL);
|
||
|
|
gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
|
||
|
|
gpio_request(GPIO_PTZ5, NULL);
|
||
|
|
gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
|
||
|
|
gpio_request(GPIO_PTZ4, NULL);
|
||
|
|
gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
|
||
|
|
|
||
|
|
__raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
|
||
|
|
|
||
|
|
/* FLCTL */
|
||
|
|
gpio_request(GPIO_FN_FCE, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF7, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF6, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF5, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF4, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF3, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF2, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF1, NULL);
|
||
|
|
gpio_request(GPIO_FN_NAF0, NULL);
|
||
|
|
gpio_request(GPIO_FN_FCDE, NULL);
|
||
|
|
gpio_request(GPIO_FN_FOE, NULL);
|
||
|
|
gpio_request(GPIO_FN_FSC, NULL);
|
||
|
|
gpio_request(GPIO_FN_FWE, NULL);
|
||
|
|
gpio_request(GPIO_FN_FRB, NULL);
|
||
|
|
|
||
|
|
__raw_writew(0, PORT_HIZCRC);
|
||
|
|
__raw_writew(0xFFFF, PORT_DRVCRA);
|
||
|
|
__raw_writew(0xFFFF, PORT_DRVCRB);
|
||
|
|
|
||
|
|
/* SDHI0 - CN3 - SD CARD */
|
||
|
|
gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
|
||
|
|
|
||
|
|
/* SDHI1 - CN7 - MICRO SD CARD */
|
||
|
|
gpio_request(GPIO_FN_SDHI1CD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI1D3, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI1D2, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI1D1, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI1D0, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI1CMD, NULL);
|
||
|
|
gpio_request(GPIO_FN_SDHI1CLK, NULL);
|
||
|
|
|
||
|
|
/* Add a clock alias for ov7725 xclk source. */
|
||
|
|
clk_add_alias(NULL, "0-0021", "video_clk", NULL);
|
||
|
|
|
||
|
|
/* Register RSTB gpio for ov7725 camera sensor. */
|
||
|
|
gpiod_add_lookup_table(&ov7725_gpios);
|
||
|
|
|
||
|
|
i2c_register_board_info(0, ap325rxa_i2c_devices,
|
||
|
|
ARRAY_SIZE(ap325rxa_i2c_devices));
|
||
|
|
|
||
|
|
/* Initialize CEU platform device separately to map memory first */
|
||
|
|
device_initialize(&ap325rxa_ceu_device.dev);
|
||
|
|
arch_setup_pdev_archdata(&ap325rxa_ceu_device);
|
||
|
|
dma_declare_coherent_memory(&ap325rxa_ceu_device.dev,
|
||
|
|
ceu_dma_membase, ceu_dma_membase,
|
||
|
|
ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
|
||
|
|
DMA_MEMORY_EXCLUSIVE);
|
||
|
|
|
||
|
|
platform_device_add(&ap325rxa_ceu_device);
|
||
|
|
|
||
|
|
return platform_add_devices(ap325rxa_devices,
|
||
|
|
ARRAY_SIZE(ap325rxa_devices));
|
||
|
|
}
|
||
|
|
arch_initcall(ap325rxa_devices_setup);
|
||
|
|
|
||
|
|
/* Return the board specific boot mode pin configuration */
|
||
|
|
static int ap325rxa_mode_pins(void)
|
||
|
|
{
|
||
|
|
/* MD0=0, MD1=0, MD2=0: Clock Mode 0
|
||
|
|
* MD3=0: 16-bit Area0 Bus Width
|
||
|
|
* MD5=1: Little Endian
|
||
|
|
* TSTMD=1, MD8=1: Test Mode Disabled
|
||
|
|
*/
|
||
|
|
return MODE_PIN5 | MODE_PIN8;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Reserve a portion of memory for CEU buffers */
|
||
|
|
static void __init ap325rxa_mv_mem_reserve(void)
|
||
|
|
{
|
||
|
|
phys_addr_t phys;
|
||
|
|
phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
|
||
|
|
|
||
|
|
phys = memblock_alloc_base(size, PAGE_SIZE, MEMBLOCK_ALLOC_ANYWHERE);
|
||
|
|
memblock_free(phys, size);
|
||
|
|
memblock_remove(phys, size);
|
||
|
|
|
||
|
|
ceu_dma_membase = phys;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct sh_machine_vector mv_ap325rxa __initmv = {
|
||
|
|
.mv_name = "AP-325RXA",
|
||
|
|
.mv_mode_pins = ap325rxa_mode_pins,
|
||
|
|
.mv_mem_reserve = ap325rxa_mv_mem_reserve,
|
||
|
|
};
|