301 lines
7.1 KiB
C
301 lines
7.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SVM_H
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#define __SVM_H
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#include <uapi/asm/svm.h>
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enum {
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INTERCEPT_INTR,
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INTERCEPT_NMI,
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INTERCEPT_SMI,
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INTERCEPT_INIT,
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INTERCEPT_VINTR,
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INTERCEPT_SELECTIVE_CR0,
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INTERCEPT_STORE_IDTR,
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INTERCEPT_STORE_GDTR,
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INTERCEPT_STORE_LDTR,
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INTERCEPT_STORE_TR,
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INTERCEPT_LOAD_IDTR,
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INTERCEPT_LOAD_GDTR,
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INTERCEPT_LOAD_LDTR,
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INTERCEPT_LOAD_TR,
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INTERCEPT_RDTSC,
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INTERCEPT_RDPMC,
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INTERCEPT_PUSHF,
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INTERCEPT_POPF,
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INTERCEPT_CPUID,
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INTERCEPT_RSM,
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INTERCEPT_IRET,
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INTERCEPT_INTn,
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INTERCEPT_INVD,
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INTERCEPT_PAUSE,
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INTERCEPT_HLT,
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INTERCEPT_INVLPG,
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INTERCEPT_INVLPGA,
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INTERCEPT_IOIO_PROT,
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INTERCEPT_MSR_PROT,
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INTERCEPT_TASK_SWITCH,
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INTERCEPT_FERR_FREEZE,
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INTERCEPT_SHUTDOWN,
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INTERCEPT_VMRUN,
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INTERCEPT_VMMCALL,
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INTERCEPT_VMLOAD,
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INTERCEPT_VMSAVE,
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INTERCEPT_STGI,
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INTERCEPT_CLGI,
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INTERCEPT_SKINIT,
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INTERCEPT_RDTSCP,
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INTERCEPT_ICEBP,
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INTERCEPT_WBINVD,
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INTERCEPT_MONITOR,
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INTERCEPT_MWAIT,
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INTERCEPT_MWAIT_COND,
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INTERCEPT_XSETBV,
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};
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struct __attribute__ ((__packed__)) vmcb_control_area {
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u32 intercept_cr;
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u32 intercept_dr;
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u32 intercept_exceptions;
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u64 intercept;
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u8 reserved_1[40];
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u16 pause_filter_thresh;
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u16 pause_filter_count;
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u64 iopm_base_pa;
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u64 msrpm_base_pa;
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u64 tsc_offset;
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u32 asid;
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u8 tlb_ctl;
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u8 reserved_2[3];
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u32 int_ctl;
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u32 int_vector;
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u32 int_state;
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u8 reserved_3[4];
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u32 exit_code;
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u32 exit_code_hi;
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u64 exit_info_1;
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u64 exit_info_2;
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u32 exit_int_info;
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u32 exit_int_info_err;
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u64 nested_ctl;
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u64 avic_vapic_bar;
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u8 reserved_4[8];
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u32 event_inj;
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u32 event_inj_err;
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u64 nested_cr3;
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u64 virt_ext;
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u32 clean;
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u32 reserved_5;
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u64 next_rip;
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u8 insn_len;
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u8 insn_bytes[15];
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u64 avic_backing_page; /* Offset 0xe0 */
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u8 reserved_6[8]; /* Offset 0xe8 */
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u64 avic_logical_id; /* Offset 0xf0 */
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u64 avic_physical_id; /* Offset 0xf8 */
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u8 reserved_7[768];
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};
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#define TLB_CONTROL_DO_NOTHING 0
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#define TLB_CONTROL_FLUSH_ALL_ASID 1
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#define TLB_CONTROL_FLUSH_ASID 3
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#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
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#define V_TPR_MASK 0x0f
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#define V_IRQ_SHIFT 8
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#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
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#define V_GIF_SHIFT 9
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#define V_GIF_MASK (1 << V_GIF_SHIFT)
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#define V_INTR_PRIO_SHIFT 16
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#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
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#define V_IGN_TPR_SHIFT 20
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#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
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#define V_INTR_MASKING_SHIFT 24
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#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
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#define V_GIF_ENABLE_SHIFT 25
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#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
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#define AVIC_ENABLE_SHIFT 31
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#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
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#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
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#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
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#define SVM_INTERRUPT_SHADOW_MASK 1
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#define SVM_IOIO_STR_SHIFT 2
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#define SVM_IOIO_REP_SHIFT 3
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#define SVM_IOIO_SIZE_SHIFT 4
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#define SVM_IOIO_ASIZE_SHIFT 7
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#define SVM_IOIO_TYPE_MASK 1
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#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
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#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
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#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
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#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
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#define SVM_VM_CR_VALID_MASK 0x001fULL
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#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
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#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
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#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
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#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
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struct __attribute__ ((__packed__)) vmcb_seg {
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u16 selector;
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u16 attrib;
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u32 limit;
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u64 base;
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};
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struct __attribute__ ((__packed__)) vmcb_save_area {
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struct vmcb_seg es;
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struct vmcb_seg cs;
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struct vmcb_seg ss;
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struct vmcb_seg ds;
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struct vmcb_seg fs;
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struct vmcb_seg gs;
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struct vmcb_seg gdtr;
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struct vmcb_seg ldtr;
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struct vmcb_seg idtr;
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struct vmcb_seg tr;
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u8 reserved_1[43];
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u8 cpl;
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u8 reserved_2[4];
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u64 efer;
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u8 reserved_3[112];
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u64 cr4;
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u64 cr3;
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u64 cr0;
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u64 dr7;
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u64 dr6;
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u64 rflags;
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u64 rip;
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u8 reserved_4[88];
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u64 rsp;
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u8 reserved_5[24];
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u64 rax;
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u64 star;
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u64 lstar;
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u64 cstar;
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u64 sfmask;
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u64 kernel_gs_base;
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u64 sysenter_cs;
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u64 sysenter_esp;
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u64 sysenter_eip;
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u64 cr2;
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u8 reserved_6[32];
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u64 g_pat;
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u64 dbgctl;
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u64 br_from;
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u64 br_to;
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u64 last_excp_from;
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u64 last_excp_to;
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};
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struct __attribute__ ((__packed__)) vmcb {
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struct vmcb_control_area control;
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struct vmcb_save_area save;
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};
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#define SVM_CPUID_FUNC 0x8000000a
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#define SVM_VM_CR_SVM_DISABLE 4
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#define SVM_SELECTOR_S_SHIFT 4
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#define SVM_SELECTOR_DPL_SHIFT 5
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#define SVM_SELECTOR_P_SHIFT 7
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#define SVM_SELECTOR_AVL_SHIFT 8
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#define SVM_SELECTOR_L_SHIFT 9
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#define SVM_SELECTOR_DB_SHIFT 10
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#define SVM_SELECTOR_G_SHIFT 11
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#define SVM_SELECTOR_TYPE_MASK (0xf)
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#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
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#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
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#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
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#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
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#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
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#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
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#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
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#define SVM_SELECTOR_WRITE_MASK (1 << 1)
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#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
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#define SVM_SELECTOR_CODE_MASK (1 << 3)
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#define INTERCEPT_CR0_READ 0
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#define INTERCEPT_CR3_READ 3
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#define INTERCEPT_CR4_READ 4
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#define INTERCEPT_CR8_READ 8
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#define INTERCEPT_CR0_WRITE (16 + 0)
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#define INTERCEPT_CR3_WRITE (16 + 3)
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#define INTERCEPT_CR4_WRITE (16 + 4)
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#define INTERCEPT_CR8_WRITE (16 + 8)
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#define INTERCEPT_DR0_READ 0
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#define INTERCEPT_DR1_READ 1
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#define INTERCEPT_DR2_READ 2
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#define INTERCEPT_DR3_READ 3
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#define INTERCEPT_DR4_READ 4
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#define INTERCEPT_DR5_READ 5
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#define INTERCEPT_DR6_READ 6
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#define INTERCEPT_DR7_READ 7
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#define INTERCEPT_DR0_WRITE (16 + 0)
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#define INTERCEPT_DR1_WRITE (16 + 1)
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#define INTERCEPT_DR2_WRITE (16 + 2)
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#define INTERCEPT_DR3_WRITE (16 + 3)
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#define INTERCEPT_DR4_WRITE (16 + 4)
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#define INTERCEPT_DR5_WRITE (16 + 5)
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#define INTERCEPT_DR6_WRITE (16 + 6)
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#define INTERCEPT_DR7_WRITE (16 + 7)
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#define SVM_EVTINJ_VEC_MASK 0xff
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#define SVM_EVTINJ_TYPE_SHIFT 8
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#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
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#define SVM_EVTINJ_VALID (1 << 31)
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#define SVM_EVTINJ_VALID_ERR (1 << 11)
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#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
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#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
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#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
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#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
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#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
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#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
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#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
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#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
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#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
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#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
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#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
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#define SVM_EXITINFO_REG_MASK 0x0F
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#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
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#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
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#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
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#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
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#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
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#define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
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#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
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#endif
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