352 lines
8.2 KiB
C
352 lines
8.2 KiB
C
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/*
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* R-Car MSTP clocks
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2015 Glider bvba
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*
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* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/renesas.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_domain.h>
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#include <linux/spinlock.h>
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/*
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* MSTP clocks. We can't use standard gate clocks as we need to poll on the
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* status register when enabling the clock.
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*/
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#define MSTP_MAX_CLOCKS 32
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/**
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* struct mstp_clock_group - MSTP gating clocks group
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*
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* @data: clocks in this group
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* @smstpcr: module stop control register
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* @mstpsr: module stop status register (optional)
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* @lock: protects writes to SMSTPCR
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* @width_8bit: registers are 8-bit, not 32-bit
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*/
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struct mstp_clock_group {
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struct clk_onecell_data data;
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void __iomem *smstpcr;
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void __iomem *mstpsr;
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spinlock_t lock;
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bool width_8bit;
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};
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/**
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* struct mstp_clock - MSTP gating clock
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* @hw: handle between common and hardware-specific interfaces
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* @bit_index: control bit index
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* @group: MSTP clocks group
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*/
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struct mstp_clock {
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struct clk_hw hw;
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u32 bit_index;
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struct mstp_clock_group *group;
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};
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#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
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static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
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u32 __iomem *reg)
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{
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return group->width_8bit ? readb(reg) : readl(reg);
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}
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static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
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u32 __iomem *reg)
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{
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group->width_8bit ? writeb(val, reg) : writel(val, reg);
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}
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static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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{
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struct mstp_clock *clock = to_mstp_clock(hw);
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struct mstp_clock_group *group = clock->group;
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u32 bitmask = BIT(clock->bit_index);
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unsigned long flags;
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unsigned int i;
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u32 value;
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spin_lock_irqsave(&group->lock, flags);
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value = cpg_mstp_read(group, group->smstpcr);
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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cpg_mstp_write(group, value, group->smstpcr);
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if (!group->mstpsr) {
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/* dummy read to ensure write has completed */
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cpg_mstp_read(group, group->smstpcr);
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barrier_data(group->smstpcr);
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}
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spin_unlock_irqrestore(&group->lock, flags);
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if (!enable || !group->mstpsr)
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return 0;
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for (i = 1000; i > 0; --i) {
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if (!(cpg_mstp_read(group, group->mstpsr) & bitmask))
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break;
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cpu_relax();
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}
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if (!i) {
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pr_err("%s: failed to enable %p[%d]\n", __func__,
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group->smstpcr, clock->bit_index);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int cpg_mstp_clock_enable(struct clk_hw *hw)
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{
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return cpg_mstp_clock_endisable(hw, true);
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}
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static void cpg_mstp_clock_disable(struct clk_hw *hw)
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{
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cpg_mstp_clock_endisable(hw, false);
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}
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static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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{
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struct mstp_clock *clock = to_mstp_clock(hw);
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struct mstp_clock_group *group = clock->group;
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u32 value;
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if (group->mstpsr)
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value = cpg_mstp_read(group, group->mstpsr);
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else
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value = cpg_mstp_read(group, group->smstpcr);
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return !(value & BIT(clock->bit_index));
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}
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static const struct clk_ops cpg_mstp_clock_ops = {
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.enable = cpg_mstp_clock_enable,
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.disable = cpg_mstp_clock_disable,
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.is_enabled = cpg_mstp_clock_is_enabled,
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};
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static struct clk * __init cpg_mstp_clock_register(const char *name,
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const char *parent_name, unsigned int index,
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struct mstp_clock_group *group)
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{
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struct clk_init_data init = {};
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struct mstp_clock *clock;
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struct clk *clk;
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &cpg_mstp_clock_ops;
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init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
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/* INTC-SYS is the module clock of the GIC, and must not be disabled */
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if (!strcmp(name, "intc-sys")) {
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pr_debug("MSTP %s setting CLK_IS_CRITICAL\n", name);
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init.flags |= CLK_IS_CRITICAL;
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}
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clock->bit_index = index;
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clock->group = group;
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clock->hw.init = &init;
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk))
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kfree(clock);
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return clk;
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}
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static void __init cpg_mstp_clocks_init(struct device_node *np)
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{
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struct mstp_clock_group *group;
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const char *idxname;
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struct clk **clks;
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unsigned int i;
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group = kzalloc(sizeof(*group), GFP_KERNEL);
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clks = kmalloc_array(MSTP_MAX_CLOCKS, sizeof(*clks), GFP_KERNEL);
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if (group == NULL || clks == NULL) {
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kfree(group);
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kfree(clks);
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return;
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}
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spin_lock_init(&group->lock);
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group->data.clks = clks;
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group->smstpcr = of_iomap(np, 0);
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group->mstpsr = of_iomap(np, 1);
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if (group->smstpcr == NULL) {
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pr_err("%s: failed to remap SMSTPCR\n", __func__);
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kfree(group);
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kfree(clks);
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return;
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}
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if (of_device_is_compatible(np, "renesas,r7s72100-mstp-clocks"))
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group->width_8bit = true;
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for (i = 0; i < MSTP_MAX_CLOCKS; ++i)
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clks[i] = ERR_PTR(-ENOENT);
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if (of_find_property(np, "clock-indices", &i))
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idxname = "clock-indices";
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else
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idxname = "renesas,clock-indices";
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for (i = 0; i < MSTP_MAX_CLOCKS; ++i) {
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const char *parent_name;
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const char *name;
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u32 clkidx;
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int ret;
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/* Skip clocks with no name. */
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ret = of_property_read_string_index(np, "clock-output-names",
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i, &name);
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if (ret < 0 || strlen(name) == 0)
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continue;
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parent_name = of_clk_get_parent_name(np, i);
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ret = of_property_read_u32_index(np, idxname, i, &clkidx);
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if (parent_name == NULL || ret < 0)
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break;
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if (clkidx >= MSTP_MAX_CLOCKS) {
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pr_err("%s: invalid clock %s %s index %u\n",
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__func__, np->name, name, clkidx);
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continue;
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}
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clks[clkidx] = cpg_mstp_clock_register(name, parent_name,
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clkidx, group);
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if (!IS_ERR(clks[clkidx])) {
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group->data.clk_num = max(group->data.clk_num,
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clkidx + 1);
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/*
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* Register a clkdev to let board code retrieve the
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* clock by name and register aliases for non-DT
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* devices.
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*
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* FIXME: Remove this when all devices that require a
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* clock will be instantiated from DT.
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*/
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clk_register_clkdev(clks[clkidx], name, NULL);
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} else {
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pr_err("%s: failed to register %s %s clock (%ld)\n",
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__func__, np->name, name, PTR_ERR(clks[clkidx]));
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}
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
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}
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CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
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int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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struct device_node *np = dev->of_node;
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struct of_phandle_args clkspec;
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struct clk *clk;
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int i = 0;
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int error;
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while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
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&clkspec)) {
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if (of_device_is_compatible(clkspec.np,
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"renesas,cpg-mstp-clocks"))
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goto found;
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/* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
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if (!strcmp(clkspec.np->name, "zb_clk"))
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goto found;
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of_node_put(clkspec.np);
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i++;
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}
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return 0;
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found:
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clk = of_clk_get_from_provider(&clkspec);
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of_node_put(clkspec.np);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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error = pm_clk_create(dev);
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if (error) {
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dev_err(dev, "pm_clk_create failed %d\n", error);
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goto fail_put;
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}
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error = pm_clk_add_clk(dev, clk);
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if (error) {
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dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
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goto fail_destroy;
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}
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return 0;
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fail_destroy:
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pm_clk_destroy(dev);
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fail_put:
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clk_put(clk);
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return error;
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}
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void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev)
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{
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if (!pm_clk_no_clocks(dev))
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pm_clk_destroy(dev);
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}
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void __init cpg_mstp_add_clk_domain(struct device_node *np)
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{
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struct generic_pm_domain *pd;
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u32 ncells;
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if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
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pr_warn("%pOF lacks #power-domain-cells\n", np);
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return;
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}
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pd = kzalloc(sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return;
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pd->name = np->name;
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pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
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GENPD_FLAG_ACTIVE_WAKEUP;
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pd->attach_dev = cpg_mstp_attach_dev;
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pd->detach_dev = cpg_mstp_detach_dev;
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pm_genpd_init(pd, &pm_domain_always_on_gov, false);
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of_genpd_add_provider_simple(np, pd);
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}
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