408 lines
9.1 KiB
C
408 lines
9.1 KiB
C
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/*
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* clk-flexgen.c
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*
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* Copyright (C) ST-Microelectronics SA 2013
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* Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
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* License terms: GNU General Public License (GPL), version 2 */
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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struct clkgen_data {
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unsigned long flags;
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bool mode;
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};
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struct flexgen {
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struct clk_hw hw;
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/* Crossbar */
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struct clk_mux mux;
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/* Pre-divisor's gate */
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struct clk_gate pgate;
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/* Pre-divisor */
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struct clk_divider pdiv;
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/* Final divisor's gate */
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struct clk_gate fgate;
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/* Final divisor */
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struct clk_divider fdiv;
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/* Asynchronous mode control */
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struct clk_gate sync;
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/* hw control flags */
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bool control_mode;
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};
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#define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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static int flexgen_enable(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *pgate_hw = &flexgen->pgate.hw;
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struct clk_hw *fgate_hw = &flexgen->fgate.hw;
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__clk_hw_set_clk(pgate_hw, hw);
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__clk_hw_set_clk(fgate_hw, hw);
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clk_gate_ops.enable(pgate_hw);
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clk_gate_ops.enable(fgate_hw);
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pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw));
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return 0;
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}
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static void flexgen_disable(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *fgate_hw = &flexgen->fgate.hw;
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/* disable only the final gate */
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__clk_hw_set_clk(fgate_hw, hw);
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clk_gate_ops.disable(fgate_hw);
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pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw));
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}
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static int flexgen_is_enabled(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *fgate_hw = &flexgen->fgate.hw;
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__clk_hw_set_clk(fgate_hw, hw);
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if (!clk_gate_ops.is_enabled(fgate_hw))
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return 0;
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return 1;
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}
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static u8 flexgen_get_parent(struct clk_hw *hw)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *mux_hw = &flexgen->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return clk_mux_ops.get_parent(mux_hw);
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}
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static int flexgen_set_parent(struct clk_hw *hw, u8 index)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *mux_hw = &flexgen->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return clk_mux_ops.set_parent(mux_hw, index);
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}
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static inline unsigned long
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clk_best_div(unsigned long parent_rate, unsigned long rate)
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{
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return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
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}
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static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long div;
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/* Round div according to exact prate and wished rate */
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div = clk_best_div(*prate, rate);
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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*prate = rate * div;
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return rate;
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}
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return *prate / div;
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}
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static unsigned long flexgen_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
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struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
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unsigned long mid_rate;
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__clk_hw_set_clk(pdiv_hw, hw);
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__clk_hw_set_clk(fdiv_hw, hw);
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mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
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return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
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}
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static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct flexgen *flexgen = to_flexgen(hw);
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struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
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struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
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struct clk_hw *sync_hw = &flexgen->sync.hw;
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struct clk_gate *config = to_clk_gate(sync_hw);
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unsigned long div = 0;
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int ret = 0;
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u32 reg;
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__clk_hw_set_clk(pdiv_hw, hw);
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__clk_hw_set_clk(fdiv_hw, hw);
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if (flexgen->control_mode) {
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reg = readl(config->reg);
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reg &= ~BIT(config->bit_idx);
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writel(reg, config->reg);
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}
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div = clk_best_div(parent_rate, rate);
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/*
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* pdiv is mainly targeted for low freq results, while fdiv
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* should be used for div <= 64. The other way round can
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* lead to 'duty cycle' issues.
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*/
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if (div <= 64) {
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clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate);
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ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div);
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} else {
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clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
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ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div);
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}
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return ret;
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}
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static const struct clk_ops flexgen_ops = {
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.enable = flexgen_enable,
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.disable = flexgen_disable,
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.is_enabled = flexgen_is_enabled,
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.get_parent = flexgen_get_parent,
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.set_parent = flexgen_set_parent,
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.round_rate = flexgen_round_rate,
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.recalc_rate = flexgen_recalc_rate,
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.set_rate = flexgen_set_rate,
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};
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static struct clk *clk_register_flexgen(const char *name,
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const char **parent_names, u8 num_parents,
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void __iomem *reg, spinlock_t *lock, u32 idx,
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unsigned long flexgen_flags, bool mode) {
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struct flexgen *fgxbar;
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struct clk *clk;
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struct clk_init_data init = {};
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u32 xbar_shift;
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void __iomem *xbar_reg, *fdiv_reg;
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fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
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if (!fgxbar)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &flexgen_ops;
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init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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xbar_reg = reg + 0x18 + (idx & ~0x3);
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xbar_shift = (idx % 4) * 0x8;
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fdiv_reg = reg + 0x164 + idx * 4;
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/* Crossbar element config */
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fgxbar->mux.lock = lock;
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fgxbar->mux.mask = BIT(6) - 1;
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fgxbar->mux.reg = xbar_reg;
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fgxbar->mux.shift = xbar_shift;
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fgxbar->mux.table = NULL;
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/* Pre-divider's gate config (in xbar register)*/
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fgxbar->pgate.lock = lock;
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fgxbar->pgate.reg = xbar_reg;
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fgxbar->pgate.bit_idx = xbar_shift + 6;
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/* Pre-divider config */
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fgxbar->pdiv.lock = lock;
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fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
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fgxbar->pdiv.width = 10;
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/* Final divider's gate config */
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fgxbar->fgate.lock = lock;
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fgxbar->fgate.reg = fdiv_reg;
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fgxbar->fgate.bit_idx = 6;
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/* Final divider config */
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fgxbar->fdiv.lock = lock;
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fgxbar->fdiv.reg = fdiv_reg;
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fgxbar->fdiv.width = 6;
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/* Final divider sync config */
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fgxbar->sync.lock = lock;
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fgxbar->sync.reg = fdiv_reg;
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fgxbar->sync.bit_idx = 7;
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fgxbar->control_mode = mode;
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fgxbar->hw.init = &init;
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clk = clk_register(NULL, &fgxbar->hw);
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if (IS_ERR(clk))
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kfree(fgxbar);
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else
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pr_debug("%s: parent %s rate %u\n",
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__clk_get_name(clk),
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__clk_get_name(clk_get_parent(clk)),
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(unsigned int)clk_get_rate(clk));
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return clk;
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}
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static const char ** __init flexgen_get_parents(struct device_node *np,
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int *num_parents)
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{
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const char **parents;
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unsigned int nparents;
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nparents = of_clk_get_parent_count(np);
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if (WARN_ON(!nparents))
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return NULL;
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parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
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if (!parents)
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return NULL;
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*num_parents = of_clk_parent_fill(np, parents, nparents);
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return parents;
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}
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static const struct clkgen_data clkgen_audio = {
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.flags = CLK_SET_RATE_PARENT,
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};
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static const struct clkgen_data clkgen_video = {
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.flags = CLK_SET_RATE_PARENT,
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.mode = 1,
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};
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static const struct of_device_id flexgen_of_match[] = {
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{
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.compatible = "st,flexgen-audio",
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.data = &clkgen_audio,
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},
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{
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.compatible = "st,flexgen-video",
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.data = &clkgen_video,
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},
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{}
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};
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static void __init st_of_flexgen_setup(struct device_node *np)
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{
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struct device_node *pnode;
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void __iomem *reg;
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struct clk_onecell_data *clk_data;
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const char **parents;
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int num_parents, i;
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spinlock_t *rlock = NULL;
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const struct of_device_id *match;
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struct clkgen_data *data = NULL;
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unsigned long flex_flags = 0;
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int ret;
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bool clk_mode = 0;
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pnode = of_get_parent(np);
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if (!pnode)
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return;
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reg = of_iomap(pnode, 0);
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if (!reg)
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return;
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parents = flexgen_get_parents(np, &num_parents);
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if (!parents) {
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iounmap(reg);
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return;
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}
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match = of_match_node(flexgen_of_match, np);
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if (match) {
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data = (struct clkgen_data *)match->data;
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flex_flags = data->flags;
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clk_mode = data->mode;
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}
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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goto err;
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ret = of_property_count_strings(np, "clock-output-names");
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if (ret <= 0) {
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pr_err("%s: Failed to get number of output clocks (%d)",
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__func__, clk_data->clk_num);
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goto err;
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}
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clk_data->clk_num = ret;
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clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
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GFP_KERNEL);
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if (!clk_data->clks)
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goto err;
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rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
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if (!rlock)
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goto err;
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spin_lock_init(rlock);
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for (i = 0; i < clk_data->clk_num; i++) {
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struct clk *clk;
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const char *clk_name;
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if (of_property_read_string_index(np, "clock-output-names",
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i, &clk_name)) {
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break;
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}
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flex_flags &= ~CLK_IS_CRITICAL;
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of_clk_detect_critical(np, i, &flex_flags);
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/*
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* If we read an empty clock name then the output is unused
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*/
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if (*clk_name == '\0')
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continue;
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clk = clk_register_flexgen(clk_name, parents, num_parents,
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reg, rlock, i, flex_flags, clk_mode);
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if (IS_ERR(clk))
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goto err;
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clk_data->clks[i] = clk;
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}
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kfree(parents);
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of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
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return;
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err:
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iounmap(reg);
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if (clk_data)
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kfree(clk_data->clks);
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kfree(clk_data);
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kfree(parents);
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kfree(rlock);
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}
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CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
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