130 lines
3.7 KiB
C
130 lines
3.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __HELIO_DVFSRC_QOS_H
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#define __HELIO_DVFSRC_QOS_H
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#include <linux/delay.h>
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#include <linux/devfreq.h>
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#include <linux/io.h>
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#include "helio-dvfsrc-smc-control.h"
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#define dvfsrc_wait_for_completion(condition, timeout) \
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({ \
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int ret = 0; \
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if (is_dvfsrc_enabled()) \
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ret = 1; \
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while (!(condition) && ret > 0) { \
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if (ret++ >= timeout) \
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ret = -EBUSY; \
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udelay(1); \
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} \
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ret; \
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})
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enum {
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DVFSRC_QOS_RESERVED = 0,
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DVFSRC_QOS_MEMORY_BANDWIDTH,
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DVFSRC_QOS_CPU_MEMORY_BANDWIDTH,
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DVFSRC_QOS_GPU_MEMORY_BANDWIDTH,
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DVFSRC_QOS_MM_MEMORY_BANDWIDTH,
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DVFSRC_QOS_OTHER_MEMORY_BANDWIDTH,
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DVFSRC_QOS_DDR_OPP,
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DVFSRC_QOS_VCORE_OPP,
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DVFSRC_QOS_SCP_VCORE_REQUEST,
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DVFSRC_QOS_POWER_MODEL_DDR_REQUEST,
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DVFSRC_QOS_POWER_MODEL_VCORE_REQUEST,
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DVFSRC_QOS_VCORE_DVFS_FORCE_OPP,
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DVFSRC_QOS_ISP_HRT_BANDWIDTH,
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DVFSRC_QOS_APU_MEMORY_BANDWIDTH,
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/* insert new ID */
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DVFSRC_QOS_NUM_CLASSES,
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};
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/* met profile table index */
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enum met_info_index {
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INFO_OPP_IDX = 0,
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INFO_FREQ_IDX,
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INFO_VCORE_IDX,
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INFO_SPM_LEVEL_IDX,
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INFO_MAX,
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};
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struct reg_config {
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u32 offset;
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u32 val;
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};
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struct helio_dvfsrc {
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int irq;
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struct device *dev;
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bool qos_enabled;
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bool dvfsrc_enabled;
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int dvfsrc_flag;
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void __iomem *regs;
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void __iomem *spm_regs;
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void __iomem *sram_regs;
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struct notifier_block mtk_pm_qos_memory_bw_nb;
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struct notifier_block mtk_pm_qos_cpu_memory_bw_nb;
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struct notifier_block mtk_pm_qos_gpu_memory_bw_nb;
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struct notifier_block mtk_pm_qos_mm_memory_bw_nb;
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struct notifier_block mtk_pm_qos_other_memory_bw_nb;
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struct notifier_block mtk_pm_qos_ddr_opp_nb;
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struct notifier_block mtk_pm_qos_vcore_opp_nb;
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struct notifier_block mtk_pm_qos_scp_vcore_request_nb;
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struct notifier_block mtk_pm_qos_power_model_ddr_request_nb;
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struct notifier_block mtk_pm_qos_power_model_vcore_request_nb;
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struct notifier_block mtk_pm_qos_vcore_dvfs_force_opp_nb;
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struct notifier_block mtk_pm_qos_isp_hrt_bw_nb;
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struct notifier_block mtk_pm_qos_apu_memory_bw_nb;
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struct reg_config *init_config;
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bool opp_forced;
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char force_start[20];
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char force_end[20];
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int (*suspend)(struct helio_dvfsrc *dvfsrc_dev);
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int (*resume)(struct helio_dvfsrc *dvfsrc_dev);
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};
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extern int is_dvfsrc_enabled(void);
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extern int is_dvfsrc_qos_enabled(void);
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extern void helio_dvfsrc_qos_init_done(void);
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extern void helio_dvfsrc_enable(int dvfsrc_en);
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extern void helio_dvfsrc_flag_set(int flag);
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extern int helio_dvfsrc_flag_get(void);
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extern u32 dvfsrc_dump_reg(char *ptr, u32 count);
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extern u32 dvfsrc_read(u32 offset);
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extern u32 spm_reg_read(u32 offset);
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extern void dvfsrc_write(u32 offset, u32 val);
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extern void dvfsrc_opp_table_init(void);
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extern int helio_dvfsrc_add_interface(struct device *dev);
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extern void helio_dvfsrc_sspm_ipi_init(int dvfsrc_en);
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extern void helio_dvfsrc_remove_interface(struct device *dev);
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extern void dvfsrc_opp_level_mapping(void);
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extern void get_opp_info(char *p);
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extern void get_dvfsrc_reg(char *p);
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extern void get_dvfsrc_record(char *p);
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extern void vcorefs_trace_qos(void);
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extern void helio_dvfsrc_platform_pre_init(struct helio_dvfsrc *dvfsrc);
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extern int helio_dvfsrc_config(struct helio_dvfsrc *dvfsrc);
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extern int commit_data(int type, int data, int check_spmfw);
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extern void dvfsrc_enable_level_intr(int en);
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extern void get_spm_reg(char *p);
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extern int vcore_pmic_to_uv(int pmic_val);
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extern int vcore_uv_to_pmic(int vcore_uv);
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extern int helio_dvfsrc_level_mask_get(void);
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extern int helio_dvfsrc_level_mask_set(bool en, int level);
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extern void mtk_pm_qos_trace_dbg_show_request(int mtk_pm_qos_class);
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extern void mtk_pm_qos_trace_dbg_dump(int mtk_pm_qos_class);
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#endif /* __HELIO_DVFSRC_QOS_H */
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