294 lines
9.2 KiB
C
294 lines
9.2 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef KFD_DBGMGR_H_
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#define KFD_DBGMGR_H_
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#include "kfd_priv.h"
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/* must align with hsakmttypes definition */
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#pragma pack(push, 4)
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enum HSA_DBG_WAVEOP {
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HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */
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HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */
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HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */
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HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter dbg mode */
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HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take a trap */
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HSA_DBG_NUM_WAVEOP = 5,
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HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF
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};
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enum HSA_DBG_WAVEMODE {
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/* send command to a single wave */
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HSA_DBG_WAVEMODE_SINGLE = 0,
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/*
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* Broadcast to all wavefronts of all processes is not
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* supported for HSA user mode
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*/
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/* send to waves within current process */
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HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2,
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/* send to waves within current process on CU */
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HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3,
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HSA_DBG_NUM_WAVEMODE = 3,
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HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF
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};
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enum HSA_DBG_WAVEMSG_TYPE {
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HSA_DBG_WAVEMSG_AUTO = 0,
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HSA_DBG_WAVEMSG_USER = 1,
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HSA_DBG_WAVEMSG_ERROR = 2,
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HSA_DBG_NUM_WAVEMSG,
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HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF
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};
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enum HSA_DBG_WATCH_MODE {
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HSA_DBG_WATCH_READ = 0, /* Read operations only */
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HSA_DBG_WATCH_NONREAD = 1, /* Write or Atomic operations only */
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HSA_DBG_WATCH_ATOMIC = 2, /* Atomic Operations only */
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HSA_DBG_WATCH_ALL = 3, /* Read, Write or Atomic operations */
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HSA_DBG_WATCH_NUM,
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HSA_DBG_WATCH_SIZE = 0xFFFFFFFF
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};
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/* This structure is hardware specific and may change in the future */
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struct HsaDbgWaveMsgAMDGen2 {
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union {
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struct ui32 {
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uint32_t UserData:8; /* user data */
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uint32_t ShaderArray:1; /* Shader array */
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uint32_t Priv:1; /* Privileged */
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uint32_t Reserved0:4; /* Reserved, should be 0 */
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uint32_t WaveId:4; /* wave id */
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uint32_t SIMD:2; /* SIMD id */
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uint32_t HSACU:4; /* Compute unit */
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uint32_t ShaderEngine:2;/* Shader engine */
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uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */
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uint32_t Reserved1:4; /* Reserved, should be 0 */
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} ui32;
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uint32_t Value;
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};
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uint32_t Reserved2;
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};
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union HsaDbgWaveMessageAMD {
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struct HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2;
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/* for future HsaDbgWaveMsgAMDGen3; */
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};
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struct HsaDbgWaveMessage {
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void *MemoryVA; /* ptr to associated host-accessible data */
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union HsaDbgWaveMessageAMD DbgWaveMsg;
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};
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/*
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* TODO: This definitions to be MOVED to kfd_event, once it is implemented.
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*
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* HSA sync primitive, Event and HW Exception notification API definitions.
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* The API functions allow the runtime to define a so-called sync-primitive,
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* a SW object combining a user-mode provided "syncvar" and a scheduler event
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* that can be signaled through a defined GPU interrupt. A syncvar is
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* a process virtual memory location of a certain size that can be accessed
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* by CPU and GPU shader code within the process to set and query the content
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* within that memory. The definition of the content is determined by the HSA
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* runtime and potentially GPU shader code interfacing with the HSA runtime.
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* The syncvar values may be commonly written through an PM4 WRITE_DATA packet
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* in the user mode instruction stream. The OS scheduler event is typically
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* associated and signaled by an interrupt issued by the GPU, but other HSA
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* system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced
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* by the KFD by this mechanism, too.
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*/
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/* these are the new definitions for events */
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enum HSA_EVENTTYPE {
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HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */
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HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */
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HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change
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* (start/stop)
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*/
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HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */
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HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */
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HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */
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HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */
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HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state
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* (EOP pm4)
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*/
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/* ... */
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HSA_EVENTTYPE_MAXID,
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HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF
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};
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/* Sub-definitions for various event types: Syncvar */
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struct HsaSyncVar {
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union SyncVar {
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void *UserData; /* pointer to user mode data */
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uint64_t UserDataPtrValue; /* 64bit compatibility of value */
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} SyncVar;
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uint64_t SyncVarSize;
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};
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/* Sub-definitions for various event types: NodeChange */
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enum HSA_EVENTTYPE_NODECHANGE_FLAGS {
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HSA_EVENTTYPE_NODECHANGE_ADD = 0,
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HSA_EVENTTYPE_NODECHANGE_REMOVE = 1,
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HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF
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};
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struct HsaNodeChange {
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/* HSA node added/removed on the platform */
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enum HSA_EVENTTYPE_NODECHANGE_FLAGS Flags;
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};
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/* Sub-definitions for various event types: DeviceStateChange */
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enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS {
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/* device started (and available) */
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HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0,
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/* device stopped (i.e. unavailable) */
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HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1,
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HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF
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};
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enum HSA_DEVICE {
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HSA_DEVICE_CPU = 0,
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HSA_DEVICE_GPU = 1,
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MAX_HSA_DEVICE = 2
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};
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struct HsaDeviceStateChange {
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uint32_t NodeId; /* F-NUMA node that contains the device */
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enum HSA_DEVICE Device; /* device type: GPU or CPU */
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enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; /* event flags */
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};
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struct HsaEventData {
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enum HSA_EVENTTYPE EventType; /* event type */
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union EventData {
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/*
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* return data associated with HSA_EVENTTYPE_SIGNAL
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* and other events
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*/
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struct HsaSyncVar SyncVar;
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/* data associated with HSA_EVENTTYPE_NODE_CHANGE */
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struct HsaNodeChange NodeChangeState;
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/* data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE */
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struct HsaDeviceStateChange DeviceState;
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} EventData;
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/* the following data entries are internal to the KFD & thunk itself */
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/* internal thunk store for Event data (OsEventHandle) */
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uint64_t HWData1;
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/* internal thunk store for Event data (HWAddress) */
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uint64_t HWData2;
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/* internal thunk store for Event data (HWData) */
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uint32_t HWData3;
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};
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struct HsaEventDescriptor {
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/* event type to allocate */
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enum HSA_EVENTTYPE EventType;
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/* H-NUMA node containing GPU device that is event source */
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uint32_t NodeId;
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/* pointer to user mode syncvar data, syncvar->UserDataPtrValue
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* may be NULL
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*/
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struct HsaSyncVar SyncVar;
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};
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struct HsaEvent {
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uint32_t EventId;
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struct HsaEventData EventData;
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};
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#pragma pack(pop)
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enum DBGDEV_TYPE {
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DBGDEV_TYPE_ILLEGAL = 0,
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DBGDEV_TYPE_NODIQ = 1,
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DBGDEV_TYPE_DIQ = 2,
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DBGDEV_TYPE_TEST = 3
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};
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struct dbg_address_watch_info {
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struct kfd_process *process;
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enum HSA_DBG_WATCH_MODE *watch_mode;
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uint64_t *watch_address;
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uint64_t *watch_mask;
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struct HsaEvent *watch_event;
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uint32_t num_watch_points;
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};
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struct dbg_wave_control_info {
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struct kfd_process *process;
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uint32_t trapId;
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enum HSA_DBG_WAVEOP operand;
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enum HSA_DBG_WAVEMODE mode;
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struct HsaDbgWaveMessage dbgWave_msg;
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};
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struct kfd_dbgdev {
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/* The device that owns this data. */
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struct kfd_dev *dev;
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/* kernel queue for DIQ */
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struct kernel_queue *kq;
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/* a pointer to the pqm of the calling process */
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struct process_queue_manager *pqm;
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/* type of debug device ( DIQ, non DIQ, etc. ) */
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enum DBGDEV_TYPE type;
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/* virtualized function pointers to device dbg */
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int (*dbgdev_register)(struct kfd_dbgdev *dbgdev);
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int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev);
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int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev,
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struct dbg_address_watch_info *adw_info);
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int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev,
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struct dbg_wave_control_info *wac_info);
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};
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struct kfd_dbgmgr {
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unsigned int pasid;
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struct kfd_dev *dev;
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struct kfd_dbgdev *dbgdev;
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};
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/* prototypes for debug manager functions */
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struct mutex *kfd_get_dbgmgr_mutex(void);
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void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr);
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bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev);
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long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
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long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
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long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
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struct dbg_wave_control_info *wac_info);
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long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
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struct dbg_address_watch_info *adw_info);
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#endif /* KFD_DBGMGR_H_ */
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