481 lines
13 KiB
C
481 lines
13 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "pp_debug.h"
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#include <linux/errno.h>
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#include "hwmgr.h"
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#include "hardwaremanager.h"
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#include "power_state.h"
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#define TEMP_RANGE_MIN (0)
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#define TEMP_RANGE_MAX (80 * 1000)
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#define PHM_FUNC_CHECK(hw) \
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do { \
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if ((hw) == NULL || (hw)->hwmgr_func == NULL) \
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return -EINVAL; \
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} while (0)
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int phm_setup_asic(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->asic_setup)
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return hwmgr->hwmgr_func->asic_setup(hwmgr);
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return 0;
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}
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int phm_power_down_asic(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->power_off_asic)
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return hwmgr->hwmgr_func->power_off_asic(hwmgr);
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return 0;
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}
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int phm_set_power_state(struct pp_hwmgr *hwmgr,
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const struct pp_hw_power_state *pcurrent_state,
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const struct pp_hw_power_state *pnew_power_state)
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{
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struct phm_set_power_state_input states;
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PHM_FUNC_CHECK(hwmgr);
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states.pcurrent_state = pcurrent_state;
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states.pnew_state = pnew_power_state;
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if (NULL != hwmgr->hwmgr_func->power_state_set)
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return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
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return 0;
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}
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int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = NULL;
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int ret = -EINVAL;;
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PHM_FUNC_CHECK(hwmgr);
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adev = hwmgr->adev;
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if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)) {
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pr_info("dpm has been enabled\n");
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return 0;
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}
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if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
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ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
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return ret;
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}
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int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
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{
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int ret = -EINVAL;
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PHM_FUNC_CHECK(hwmgr);
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if (!smum_is_dpm_running(hwmgr)) {
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pr_info("dpm has been disabled\n");
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return 0;
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}
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if (hwmgr->hwmgr_func->dynamic_state_management_disable)
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ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
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return ret;
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}
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int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
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{
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int ret = 0;
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->force_dpm_level != NULL)
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ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
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return ret;
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}
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int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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struct pp_power_state *adjusted_ps,
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const struct pp_power_state *current_ps)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
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return hwmgr->hwmgr_func->apply_state_adjust_rules(
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hwmgr,
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adjusted_ps,
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current_ps);
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return 0;
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}
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int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL)
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return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr);
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return 0;
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}
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int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
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return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
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return 0;
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}
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int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating)
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return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr);
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return 0;
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}
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int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
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return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
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return 0;
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}
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int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->pre_display_config_changed)
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hwmgr->hwmgr_func->pre_display_config_changed(hwmgr);
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return 0;
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}
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int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->display_config_changed)
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hwmgr->hwmgr_func->display_config_changed(hwmgr);
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return 0;
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}
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int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
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hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
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return 0;
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}
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int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
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return -EINVAL;
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return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
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}
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int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
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return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
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return 0;
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}
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/**
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* Initializes the thermal controller subsystem.
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*
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* @param pHwMgr the address of the powerplay hardware manager.
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* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher.
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*/
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int phm_start_thermal_controller(struct pp_hwmgr *hwmgr)
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{
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int ret = 0;
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struct PP_TemperatureRange range = {TEMP_RANGE_MIN, TEMP_RANGE_MAX};
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struct amdgpu_device *adev = hwmgr->adev;
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if (hwmgr->hwmgr_func->get_thermal_temperature_range)
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hwmgr->hwmgr_func->get_thermal_temperature_range(
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hwmgr, &range);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_ThermalController)
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&& hwmgr->hwmgr_func->start_thermal_controller != NULL)
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ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
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adev->pm.dpm.thermal.min_temp = range.min;
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adev->pm.dpm.thermal.max_temp = range.max;
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return ret;
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}
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bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
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return false;
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return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
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}
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int phm_check_states_equal(struct pp_hwmgr *hwmgr,
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const struct pp_hw_power_state *pstate1,
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const struct pp_hw_power_state *pstate2,
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bool *equal)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->check_states_equal == NULL)
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return -EINVAL;
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return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
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}
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int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
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const struct amd_pp_display_configuration *display_config)
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{
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int index = 0;
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int number_of_active_display = 0;
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PHM_FUNC_CHECK(hwmgr);
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if (display_config == NULL)
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return -EINVAL;
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if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
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hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
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for (index = 0; index < display_config->num_path_including_non_display; index++) {
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if (display_config->displays[index].controller_id != 0)
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number_of_active_display++;
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}
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if (NULL != hwmgr->hwmgr_func->set_active_display_count)
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hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
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if (hwmgr->hwmgr_func->store_cc6_data == NULL)
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return -EINVAL;
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/* TODO: pass other display configuration in the future */
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if (hwmgr->hwmgr_func->store_cc6_data)
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hwmgr->hwmgr_func->store_cc6_data(hwmgr,
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display_config->cpu_pstate_separation_time,
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display_config->cpu_cc6_disable,
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display_config->cpu_pstate_disable,
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display_config->nb_pstate_switch_disable);
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return 0;
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}
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int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
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struct amd_pp_simple_clock_info *info)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
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return -EINVAL;
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return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
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}
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int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
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return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
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return 0;
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}
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int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
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PHM_PerformanceLevelDesignation designation, uint32_t index,
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PHM_PerformanceLevel *level)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (hwmgr->hwmgr_func->get_performance_level == NULL)
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return -EINVAL;
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return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
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}
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/**
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* Gets Clock Info.
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*
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* @param pHwMgr the address of the powerplay hardware manager.
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* @param pPowerState the address of the Power State structure.
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* @param pClockInfo the address of PP_ClockInfo structure where the result will be returned.
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* @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the back-end.
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*/
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int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
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PHM_PerformanceLevelDesignation designation)
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{
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int result;
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PHM_PerformanceLevel performance_level;
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||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
|
||
|
|
PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
|
||
|
|
|
||
|
|
result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
|
||
|
|
|
||
|
|
PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
|
||
|
|
|
||
|
|
|
||
|
|
pclock_info->min_mem_clk = performance_level.memory_clock;
|
||
|
|
pclock_info->min_eng_clk = performance_level.coreClock;
|
||
|
|
pclock_info->min_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
|
||
|
|
|
||
|
|
|
||
|
|
result = phm_get_performance_level(hwmgr, state, designation,
|
||
|
|
(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
|
||
|
|
|
||
|
|
PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);
|
||
|
|
|
||
|
|
pclock_info->max_mem_clk = performance_level.memory_clock;
|
||
|
|
pclock_info->max_eng_clk = performance_level.coreClock;
|
||
|
|
pclock_info->max_bus_bandwidth = performance_level.nonLocalMemoryFreq * performance_level.nonLocalMemoryWidth;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
|
||
|
|
enum amd_pp_clock_type type,
|
||
|
|
struct pp_clock_levels_with_latency *clocks)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
|
||
|
|
enum amd_pp_clock_type type,
|
||
|
|
struct pp_clock_levels_with_voltage *clocks)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
|
||
|
|
void *clock_ranges)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
|
||
|
|
clock_ranges);
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
|
||
|
|
struct pp_display_clock_request *clock)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (!hwmgr->hwmgr_func->display_clock_voltage_request)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
|
||
|
|
}
|
||
|
|
|
||
|
|
int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
|
||
|
|
{
|
||
|
|
PHM_FUNC_CHECK(hwmgr);
|
||
|
|
|
||
|
|
if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);
|
||
|
|
}
|