121 lines
4 KiB
C
121 lines
4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef HDCP_TX_H
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#define HDCP_TX_H
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#include "mtk_dp_common.h"
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#ifdef DPTX_HDCP_ENABLE
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#define HDCP2_RXSTATUS_SIZE 1
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#define HDCP2_RTX_SIZE 8
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#define HDCP2_RRX_SIZE 8
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#define HDCP2_TXCAPS_SIZE 3
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#define HDCP2_RXCAPS_SIZE 3
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#define HDCP2_M_SIZE 16
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#define HDCP2_KD_SIZE 32
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#define HDCP2_CERTRX_SIZE 522
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#define HDCP2_EKPUBKM_SIZE 128
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#define HDCP2_EKHKM_SIZE 16
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#define HDCP2_KM_SIZE 16
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#define HDCP2_KH_SIZE 16
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#define HDCP2_RN_SIZE 8
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#define HDCP2_LPRIME_SIZE 32
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#define HDCP2_EDKEYKS_SIZE 16
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#define HDCP2_KS_SIZE 16
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#define HDCP2_RIV_SIZE 8
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#define HDCP2_RXINFO_SIZE 2
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#define HDCP2_SEQ_NUM_V_SIZE 3
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#define HDCP2_RECVID_SIZE 5
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#define HDCP2_VPRIME_SIZE 16
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#define HDCP2_RECV_ID_LIST_SIZE 155
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#define HDCP2_SEQ_NUM_M_SIZE 3
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#define HDCP2_STREAMID_TYPE_SIZE 2
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#define HDCP2_K_SIZE 2
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#define HDCP2_REP_MPRIME_SIZE 32
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#define HDCP2_HPRIME_SIZE 32
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#define HDCP2_RX_ENCKEY_SIZE 104
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#define HDCP2_TX_ENCKEY_SIZE 448
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#define HDCP2_LC128_SIZE 16
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#define HDCP2_KPUBRX_MODULUS_SIZE 128
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#define HDCP2_KPUBRX_EXPONENT_SIZE 3
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#define HDCP2_KPUBRX_RESERVED_SIZE 2
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#define HDCP2_MAX_DEVICE_COUNT 31
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#define HDCP2_MAX_DEPTH_LEVEL 4
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#define HDCP2_KPUB_SIZE 384
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//timeout relative
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#define HDCP2_AKESENDCERT_WDT 100 // 100ms
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#define HDCP2_AKESENDHPRIME_NO_STORED_WDT 1000 // 1sec
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#define HDCP2_AKESENDHPRIME_STORED_WDT 200 // 200ms
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#define HDCP2_AKESENDPAIRINGINFO_WDT 200 // 200ms
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#define HDCP2_LCSENDLPRIME_WDT 7 // 7ms
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#define HDCP2_ENC_EN_TIMER 200 // 200 ms
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#define HDCP2_REPAUTHSENDRECVID_WDT 3000 // 3 sec
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#define HDCP2_REP_SEND_ACK 2000 // 2 Sec
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#define HDCP2_REPAUTHSTREAMRDY_WDT 100 // 100 ms
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//Patch for QD980 LLCTS
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#define HDCP2_TX_RETRY_CNT 3
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#define HDCP2_TX_LC_RETRY_CNT 1023
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#define HDCP2_STREAM_MANAGE_RETRY_CNT 8
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enum ENUM_HDCP2TX_MAIN_STATE {
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HDCP2_MS_H1P1 = 0,
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HDCP2_MS_A0F0 = 1,
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HDCP2_MS_A1F1 = 2,
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HDCP2_MS_A2F2 = 3,
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HDCP2_MS_A3F3 = 4,
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HDCP2_MS_A4F4 = 5,
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HDCP2_MS_A5F5 = 6,
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HDCP2_MS_A6F6 = 7,
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HDCP2_MS_A7F7 = 8,
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HDCP2_MS_A8F8 = 9,
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HDCP2_MS_A9F9 = 10
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};
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enum ENUM_HDCP2_MSG_LIST {
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HDCP2_MSG_ZERO = 0,
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HDCP2_MSG_AKE_INIT = 1,
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HDCP2_MSG_AKE_SEND_CERT = 2,
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HDCP2_MSG_AKE_NO_STORED_KM = 3,
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HDCP2_MSG_AKE_STORED_KM = 4,
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HDCP2_MSG_AKE_SEND_H_PRIME = 5,
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HDCP2_MSG_AKE_SEND_PAIRING_INFO = 6,
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HDCP2_MSG_LC_INIT = 7,
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HDCP2_MSG_LC_SEND_L_PRIME = 8,
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HDCP2_MSG_SKE_SEND_EKS = 9,
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HDCP2_MSG_REPAUTH_SEND_RECVID_LIST = 10,
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HDCP2_MSG_REPAUTH_VERIFY_RECVID_LIST = 11,
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HDCP2_MSG_REPAUTH_SEND_ACK = 12,
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HDCP2_MSG_REPAUTH_STREAM_MANAGE = 13,
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HDCP2_MSG_REPAUTH_STREAM_READY = 14,
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HDCP2_MSG_AUTH_FAIL = 15,
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HDCP2_MSG_AUTH_DONE = 16,
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};
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struct HDCP2_PAIRING_INFO {
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BYTE u8M[HDCP2_M_SIZE];
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BYTE u8EkhKM[HDCP2_EKHKM_SIZE];
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};
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enum ENUM_HDCP_ERR_CODE {
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HDCP_ERR_NONE = 0,
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HDCP_ERR_UNKNOWN_STATE,
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HDCP_ERR_SEND_MSG_FAIL,
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HDCP_ERR_RESPONSE_TIMEROUT,
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HDCP_ERR_PROCESS_FAIL
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};
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int HDCPTx_Hdcp2FSM(struct mtk_dp *mtk_dp);
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void mdrv_DPTx_HDCP2_SetStartAuth(struct mtk_dp *mtk_dp, bool bEnable);
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bool mdrv_DPTx_HDCP2_Support(struct mtk_dp *mtk_dp);
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bool mdrv_DPTx_HDCP2_irq(struct mtk_dp *mtk_dp);
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#endif
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#endif //#ifndef HDCP_TX_H
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