2024-04-28 06:49:01 -07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef MTK_DRM_DRV_H
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#define MTK_DRM_DRV_H
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#include <drm/drm_fb_helper.h>
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#include <drm/mediatek_drm.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <drm/drm_atomic.h>
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_plane.h"
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#include "mtk_drm_crtc.h"
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#include "mtk_drm_ddp.h"
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#include "mtk_drm_session.h"
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#include "mtk_drm_helper.h"
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#include "mtk_notify.h"
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#define MAX_CONNECTOR 3
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#ifndef CONFIG_FPGA_EARLY_PORTING
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#define MTK_DRM_ESD_SUPPORT
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#define MTK_FB_MMDVFS_SUPPORT
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#endif
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#define MTK_DRM_FENCE_SUPPORT
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#define MTK_DRM_CMDQ_ASYNC
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#define CONFIG_MTK_DISPLAY_CMDQ
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#define MTK_FILL_MIPI_IMPEDANCE
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#if (defined(CONFIG_MACH_MT6885) || defined(CONFIG_MACH_MT6873)\
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|| defined(CONFIG_MACH_MT6893) ||\
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defined(CONFIG_MACH_MT6853) || \
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defined(CONFIG_MACH_MT6833) || \
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defined(CONFIG_MACH_MT6781)) &&\
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defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
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#define MTK_DRM_DELAY_PRESENT_FENCE
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/* Delay present fence would cause config merge */
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#endif
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#if defined(CONFIG_MACH_MT6877) || defined(CONFIG_MACH_MT6781)
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/*
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* MTK_DRM_DELAY_PRESENT_FENCE can not be defined,
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* but SF present fence must be enabled in platform dts
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*/
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#define MTK_DRM_DELAY_PRESENT_FENCE_SOF
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#endif
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#if defined(CONFIG_MACH_MT6893) || defined(CONFIG_MACH_MT6853)\
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|| defined(CONFIG_MACH_MT6877)
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#define CONFIG_MTK_DYN_SWITCH_BY_CMD
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#endif
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#ifdef CONFIG_MTK_IOMMU_V2
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#define CONFIG_MTK_DISPLAY_M4U
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#endif
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struct device;
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struct device_node;
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struct drm_crtc;
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struct drm_device;
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struct drm_property;
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struct regmap;
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struct mm_qos_request;
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struct mtk_pm_qos_request;
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struct mtk_atomic_state {
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struct drm_atomic_state base;
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struct list_head list;
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struct kref kref;
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};
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struct mtk_fake_eng_reg {
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unsigned int CG_idx;
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unsigned int CG_bit;
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bool share_port;
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};
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struct mtk_fake_eng_data {
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int fake_eng_num;
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const struct mtk_fake_eng_reg *fake_eng_reg;
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};
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struct mtk_mmsys_driver_data {
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const struct mtk_crtc_path_data *main_path_data;
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const struct mtk_crtc_path_data *ext_path_data;
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const struct mtk_crtc_path_data *third_path_data;
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enum mtk_mmsys_id mmsys_id;
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bool shadow_register;
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const struct mtk_session_mode_tb *mode_tb;
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void (*sodi_config)(struct drm_device *drm, enum mtk_ddp_comp_id id,
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struct cmdq_pkt *handle, void *data);
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const struct mtk_fake_eng_data *fake_eng_data;
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bool bypass_infra_ddr_control;
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};
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struct mtk_drm_lyeblob_ids {
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uint32_t lye_idx;
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uint32_t frame_weight;
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uint32_t hrt_num;
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int32_t ddp_blob_id;
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int32_t ref_cnt;
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int32_t ref_cnt_mask;
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int32_t free_cnt_mask;
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int32_t lye_plane_blob_id[MAX_CRTC][OVL_LAYER_NR];
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struct list_head list;
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};
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struct mtk_drm_private {
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struct drm_device *drm;
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struct device *dma_dev;
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struct device *mmsys_dev;
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#if defined(CONFIG_MTK_IOMMU_V2)
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struct ion_client *client;
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#endif
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struct drm_crtc *crtc[MAX_CRTC];
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unsigned int num_pipes;
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unsigned int session_id[MAX_SESSION_COUNT];
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unsigned int num_sessions;
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enum MTK_DRM_SESSION_MODE session_mode;
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atomic_t crtc_present[MAX_CRTC];
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atomic_t crtc_sf_present[MAX_CRTC];
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2024-04-28 06:51:13 -07:00
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atomic_t crtc_rel_present[MAX_CRTC];
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2024-04-28 06:49:01 -07:00
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struct device_node *mutex_node;
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struct device *mutex_dev;
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void __iomem *config_regs;
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resource_size_t config_regs_pa;
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void __iomem *infra_regs;
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resource_size_t infra_regs_pa;
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const struct mtk_mmsys_reg_data *reg_data;
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struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
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struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
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const struct mtk_mmsys_driver_data *data;
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struct {
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struct drm_atomic_state *state;
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struct work_struct work;
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struct mutex lock;
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} commit;
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struct drm_atomic_state *suspend_state;
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struct {
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struct work_struct work;
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struct list_head list;
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spinlock_t lock;
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} unreference;
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/* property */
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struct drm_property *crtc_property[MAX_CRTC][CRTC_PROP_MAX];
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struct drm_fb_helper fb_helper;
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struct kref kref_fb_buf;
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struct drm_gem_object *fbdev_bo;
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struct list_head lyeblob_head;
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struct mutex lyeblob_list_mutex;
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struct task_struct *fence_release_thread[MAX_CRTC-1];
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/* variable for repaint */
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struct {
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wait_queue_head_t wq;
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struct list_head job_queue;
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struct list_head job_pool;
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} repaint_data;
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struct mtk_drm_helper *helper_opt;
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atomic_t idle_need_repaint;
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atomic_t rollback_all;
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unsigned int top_clk_num;
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struct clk **top_clk;
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bool power_state;
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/* for rpo caps info */
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unsigned int rsz_in_max[2];
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#ifdef MTK_FB_MMDVFS_SUPPORT
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struct plist_head bw_request_list;
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struct plist_head hrt_request_list;
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struct mtk_pm_qos_request ddr_opp_request;
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struct mtk_pm_qos_request mm_freq_request;
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struct mm_qos_request hrt_bw_request;
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#endif
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struct pinctrl *pctrl;
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#ifdef DRM_MMPATH
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int HWC_gpid; // for mmpath auto gen
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#endif
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int need_vds_path_switch;
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int vds_path_switch_dirty;
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int vds_path_switch_done;
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int need_vds_path_switch_back;
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int vds_path_enable;
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bool need_cwb_path_disconnect;
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bool cwb_is_preempted;
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/* Due to 2nd display share 1 secure gce client, need store here */
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struct cmdq_client *ext_sec_client;
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struct mtk_uevent_dev uevent_data;
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};
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struct mtk_drm_property {
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int flags;
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char *name;
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unsigned long min;
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unsigned long max;
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unsigned long val;
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};
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struct repaint_job_t {
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struct list_head link;
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unsigned int type;
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};
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#define LCM_FPS_ARRAY_SIZE 32
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struct lcm_fps_ctx_t {
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atomic_t is_inited;
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spinlock_t lock;
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atomic_t skip_update;
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unsigned int dsi_mode;
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unsigned int head_idx;
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unsigned int num;
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unsigned int fps;
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unsigned long long last_ns;
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unsigned long long array[LCM_FPS_ARRAY_SIZE];
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};
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#define DISP_LARB_COUNT 1
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struct disp_iommu_device {
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struct platform_device *larb_pdev[DISP_LARB_COUNT];
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struct platform_device *iommu_pdev;
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unsigned int inited;
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};
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struct disp_iommu_device *disp_get_iommu_dev(void);
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extern struct platform_driver mtk_ddp_driver;
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extern struct platform_driver mtk_disp_color_driver;
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extern struct platform_driver mtk_disp_ccorr_driver;
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extern struct platform_driver mtk_disp_gamma_driver;
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extern struct platform_driver mtk_disp_aal_driver;
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extern struct platform_driver mtk_dmdp_aal_driver;
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extern struct platform_driver mtk_disp_postmask_driver;
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extern struct platform_driver mtk_disp_dither_driver;
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extern struct platform_driver mtk_disp_ovl_driver;
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extern struct platform_driver mtk_disp_rdma_driver;
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extern struct platform_driver mtk_disp_wdma_driver;
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extern struct platform_driver mtk_disp_rsz_driver;
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extern struct platform_driver mtk_dpi_driver;
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extern struct platform_driver mtk_dsi_driver;
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extern struct platform_driver mtk_mipi_tx_driver;
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extern struct platform_driver mtk_lvds_driver;
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extern struct platform_driver mtk_lvds_tx_driver;
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extern struct platform_driver mtk_disp_dsc_driver;
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extern struct lcm_fps_ctx_t lcm_fps_ctx[MAX_CRTC];
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extern struct platform_driver mtk_disp_merge_driver;
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#ifdef CONFIG_MTK_HDMI_SUPPORT
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extern struct platform_driver mtk_dp_tx_driver;
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extern struct platform_driver mtk_dp_intf_driver;
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#endif
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void mtk_atomic_state_put_queue(struct drm_atomic_state *state);
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void mtk_drm_fence_update(unsigned int fence_idx, unsigned int index);
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void drm_trigger_repaint(enum DRM_REPAINT_TYPE type,
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struct drm_device *drm_dev);
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int mtk_drm_suspend_release_fence(struct device *dev);
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void mtk_drm_suspend_release_present_fence(struct device *dev,
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unsigned int index);
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void mtk_drm_suspend_release_sf_present_fence(struct device *dev,
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unsigned int index);
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void mtk_drm_top_clk_prepare_enable(struct drm_device *drm);
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void mtk_drm_top_clk_disable_unprepare(struct drm_device *drm);
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struct mtk_panel_params *mtk_drm_get_lcm_ext_params(struct drm_crtc *crtc);
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struct mtk_panel_funcs *mtk_drm_get_lcm_ext_funcs(struct drm_crtc *crtc);
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bool mtk_drm_session_mode_is_decouple_mode(struct drm_device *dev);
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bool mtk_drm_session_mode_is_mirror_mode(struct drm_device *dev);
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bool mtk_drm_top_clk_isr_get(char *master);
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void mtk_drm_top_clk_isr_put(char *master);
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int lcm_fps_ctx_init(struct drm_crtc *crtc);
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int lcm_fps_ctx_reset(struct drm_crtc *crtc);
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int lcm_fps_ctx_update(unsigned long long cur_ns,
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unsigned int crtc_id, unsigned int mode);
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int mtk_mipi_clk_change(struct drm_crtc *crtc, unsigned int data_rate);
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void disp_drm_debug(const char *opt);
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extern int mtk_notifier_call_chain(unsigned long val, void *v);
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#endif /* MTK_DRM_DRV_H */
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