451 lines
15 KiB
C
451 lines
15 KiB
C
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_DRV_H__
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#define __MSM_DRV_H__
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/component.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/iommu.h>
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#include <linux/types.h>
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#include <linux/of_graph.h>
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#include <linux/of_device.h>
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#include <asm/sizes.h>
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#include <linux/kthread.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/msm_drm.h>
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#include <drm/drm_gem.h>
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struct msm_kms;
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struct msm_gpu;
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struct msm_mmu;
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struct msm_mdss;
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struct msm_rd_state;
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struct msm_perf_state;
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struct msm_gem_submit;
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struct msm_fence_context;
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struct msm_gem_address_space;
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struct msm_gem_vma;
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#define MAX_CRTCS 8
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#define MAX_PLANES 20
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#define MAX_ENCODERS 8
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#define MAX_BRIDGES 8
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#define MAX_CONNECTORS 8
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#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
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struct msm_file_private {
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rwlock_t queuelock;
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struct list_head submitqueues;
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int queueid;
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};
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enum msm_mdp_plane_property {
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PLANE_PROP_ZPOS,
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PLANE_PROP_ALPHA,
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PLANE_PROP_PREMULTIPLIED,
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PLANE_PROP_MAX_NUM
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};
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struct msm_vblank_ctrl {
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struct kthread_work work;
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struct list_head event_list;
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spinlock_t lock;
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};
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#define MSM_GPU_MAX_RINGS 4
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#define MAX_H_TILES_PER_DISPLAY 2
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/**
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* enum msm_display_caps - features/capabilities supported by displays
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* @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
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* @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
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* @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
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* @MSM_DISPLAY_CAP_EDID: EDID supported
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*/
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enum msm_display_caps {
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MSM_DISPLAY_CAP_VID_MODE = BIT(0),
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MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
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MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
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MSM_DISPLAY_CAP_EDID = BIT(3),
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};
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/**
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* enum msm_event_wait - type of HW events to wait for
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* @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
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* @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
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* @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
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*/
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enum msm_event_wait {
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MSM_ENC_COMMIT_DONE = 0,
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MSM_ENC_TX_COMPLETE,
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MSM_ENC_VBLANK,
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};
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/**
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* struct msm_display_topology - defines a display topology pipeline
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* @num_lm: number of layer mixers used
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* @num_enc: number of compression encoder blocks used
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* @num_intf: number of interfaces the panel is mounted on
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*/
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struct msm_display_topology {
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u32 num_lm;
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u32 num_enc;
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u32 num_intf;
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};
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/**
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* struct msm_display_info - defines display properties
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* @intf_type: DRM_MODE_CONNECTOR_ display type
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* @capabilities: Bitmask of display flags
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* @num_of_h_tiles: Number of horizontal tiles in case of split interface
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* @h_tile_instance: Controller instance used per tile. Number of elements is
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* based on num_of_h_tiles
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* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
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* used instead of panel TE in cmd mode panels
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*/
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struct msm_display_info {
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int intf_type;
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uint32_t capabilities;
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uint32_t num_of_h_tiles;
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uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
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bool is_te_using_watchdog_timer;
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};
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/* Commit/Event thread specific structure */
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struct msm_drm_thread {
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struct drm_device *dev;
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struct task_struct *thread;
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unsigned int crtc_id;
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struct kthread_worker worker;
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};
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struct msm_drm_private {
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struct drm_device *dev;
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struct msm_kms *kms;
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/* subordinate devices, if present: */
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struct platform_device *gpu_pdev;
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/* top level MDSS wrapper device (for MDP5/DPU only) */
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struct msm_mdss *mdss;
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/* possibly this should be in the kms component, but it is
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* shared by both mdp4 and mdp5..
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*/
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struct hdmi *hdmi;
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/* eDP is for mdp5 only, but kms has not been created
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* when edp_bind() and edp_init() are called. Here is the only
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* place to keep the edp instance.
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*/
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struct msm_edp *edp;
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/* DSI is shared by mdp4 and mdp5 */
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struct msm_dsi *dsi[2];
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/* when we have more than one 'msm_gpu' these need to be an array: */
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struct msm_gpu *gpu;
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struct msm_file_private *lastctx;
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struct drm_fb_helper *fbdev;
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struct msm_rd_state *rd; /* debugfs to dump all submits */
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struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
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struct msm_perf_state *perf;
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/* list of GEM objects: */
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struct list_head inactive_list;
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struct workqueue_struct *wq;
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unsigned int num_planes;
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struct drm_plane *planes[MAX_PLANES];
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unsigned int num_crtcs;
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struct drm_crtc *crtcs[MAX_CRTCS];
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struct msm_drm_thread disp_thread[MAX_CRTCS];
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struct msm_drm_thread event_thread[MAX_CRTCS];
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unsigned int num_encoders;
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struct drm_encoder *encoders[MAX_ENCODERS];
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unsigned int num_bridges;
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struct drm_bridge *bridges[MAX_BRIDGES];
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unsigned int num_connectors;
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struct drm_connector *connectors[MAX_CONNECTORS];
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/* Properties */
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struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
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/* VRAM carveout, used when no IOMMU: */
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struct {
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unsigned long size;
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dma_addr_t paddr;
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/* NOTE: mm managed at the page level, size is in # of pages
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* and position mm_node->start is in # of pages:
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*/
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struct drm_mm mm;
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spinlock_t lock; /* Protects drm_mm node allocation/removal */
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} vram;
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struct notifier_block vmap_notifier;
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struct shrinker shrinker;
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struct msm_vblank_ctrl vblank_ctrl;
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struct drm_atomic_state *pm_state;
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};
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struct msm_format {
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uint32_t pixel_format;
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};
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int msm_atomic_prepare_fb(struct drm_plane *plane,
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struct drm_plane_state *new_state);
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void msm_atomic_commit_tail(struct drm_atomic_state *state);
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struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
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void msm_atomic_state_clear(struct drm_atomic_state *state);
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void msm_atomic_state_free(struct drm_atomic_state *state);
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void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
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struct msm_gem_vma *vma, struct sg_table *sgt);
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int msm_gem_map_vma(struct msm_gem_address_space *aspace,
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struct msm_gem_vma *vma, struct sg_table *sgt, int npages);
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void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
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struct msm_gem_address_space *
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msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
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const char *name);
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int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
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void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
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void msm_gem_submit_free(struct msm_gem_submit *submit);
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int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
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struct drm_file *file);
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void msm_gem_shrinker_init(struct drm_device *dev);
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void msm_gem_shrinker_cleanup(struct drm_device *dev);
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int msm_gem_mmap_obj(struct drm_gem_object *obj,
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struct vm_area_struct *vma);
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int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
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vm_fault_t msm_gem_fault(struct vm_fault *vmf);
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uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
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int msm_gem_get_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace, uint64_t *iova);
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uint64_t msm_gem_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace);
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struct page **msm_gem_get_pages(struct drm_gem_object *obj);
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void msm_gem_put_pages(struct drm_gem_object *obj);
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void msm_gem_put_iova(struct drm_gem_object *obj,
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struct msm_gem_address_space *aspace);
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int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
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uint32_t handle, uint64_t *offset);
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struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
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void *msm_gem_prime_vmap(struct drm_gem_object *obj);
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void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
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int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
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struct reservation_object *msm_gem_prime_res_obj(struct drm_gem_object *obj);
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struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
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struct dma_buf_attachment *attach, struct sg_table *sg);
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int msm_gem_prime_pin(struct drm_gem_object *obj);
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void msm_gem_prime_unpin(struct drm_gem_object *obj);
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void *msm_gem_get_vaddr(struct drm_gem_object *obj);
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void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
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void msm_gem_put_vaddr(struct drm_gem_object *obj);
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int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
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int msm_gem_sync_object(struct drm_gem_object *obj,
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struct msm_fence_context *fctx, bool exclusive);
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void msm_gem_move_to_active(struct drm_gem_object *obj,
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struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
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void msm_gem_move_to_inactive(struct drm_gem_object *obj);
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int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
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int msm_gem_cpu_fini(struct drm_gem_object *obj);
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void msm_gem_free_object(struct drm_gem_object *obj);
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int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
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uint32_t size, uint32_t flags, uint32_t *handle);
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struct drm_gem_object *msm_gem_new(struct drm_device *dev,
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uint32_t size, uint32_t flags);
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struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
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uint32_t size, uint32_t flags);
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void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
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uint32_t flags, struct msm_gem_address_space *aspace,
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struct drm_gem_object **bo, uint64_t *iova);
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void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
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uint32_t flags, struct msm_gem_address_space *aspace,
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struct drm_gem_object **bo, uint64_t *iova);
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struct drm_gem_object *msm_gem_import(struct drm_device *dev,
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struct dma_buf *dmabuf, struct sg_table *sgt);
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int msm_framebuffer_prepare(struct drm_framebuffer *fb,
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struct msm_gem_address_space *aspace);
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void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
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struct msm_gem_address_space *aspace);
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uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
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struct msm_gem_address_space *aspace, int plane);
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struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
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const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
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struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
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struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
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struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
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int w, int h, int p, uint32_t format);
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struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
|
||
|
|
void msm_fbdev_free(struct drm_device *dev);
|
||
|
|
|
||
|
|
struct hdmi;
|
||
|
|
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
|
||
|
|
struct drm_encoder *encoder);
|
||
|
|
void __init msm_hdmi_register(void);
|
||
|
|
void __exit msm_hdmi_unregister(void);
|
||
|
|
|
||
|
|
struct msm_edp;
|
||
|
|
void __init msm_edp_register(void);
|
||
|
|
void __exit msm_edp_unregister(void);
|
||
|
|
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
|
||
|
|
struct drm_encoder *encoder);
|
||
|
|
|
||
|
|
struct msm_dsi;
|
||
|
|
#ifdef CONFIG_DRM_MSM_DSI
|
||
|
|
void __init msm_dsi_register(void);
|
||
|
|
void __exit msm_dsi_unregister(void);
|
||
|
|
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
|
||
|
|
struct drm_encoder *encoder);
|
||
|
|
#else
|
||
|
|
static inline void __init msm_dsi_register(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
static inline void __exit msm_dsi_unregister(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
|
||
|
|
struct drm_device *dev,
|
||
|
|
struct drm_encoder *encoder)
|
||
|
|
{
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void __init msm_mdp_register(void);
|
||
|
|
void __exit msm_mdp_unregister(void);
|
||
|
|
void __init msm_dpu_register(void);
|
||
|
|
void __exit msm_dpu_unregister(void);
|
||
|
|
|
||
|
|
#ifdef CONFIG_DEBUG_FS
|
||
|
|
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
|
||
|
|
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
|
||
|
|
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
|
||
|
|
int msm_debugfs_late_init(struct drm_device *dev);
|
||
|
|
int msm_rd_debugfs_init(struct drm_minor *minor);
|
||
|
|
void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
|
||
|
|
void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
|
||
|
|
const char *fmt, ...);
|
||
|
|
int msm_perf_debugfs_init(struct drm_minor *minor);
|
||
|
|
void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
|
||
|
|
#else
|
||
|
|
static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
|
||
|
|
static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
|
||
|
|
const char *fmt, ...) {}
|
||
|
|
static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
|
||
|
|
static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
|
||
|
|
int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk);
|
||
|
|
|
||
|
|
struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
|
||
|
|
const char *name);
|
||
|
|
void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
|
||
|
|
const char *dbgname);
|
||
|
|
void msm_writel(u32 data, void __iomem *addr);
|
||
|
|
u32 msm_readl(const void __iomem *addr);
|
||
|
|
|
||
|
|
struct msm_gpu_submitqueue;
|
||
|
|
int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
|
||
|
|
struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
|
||
|
|
u32 id);
|
||
|
|
int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
|
||
|
|
u32 prio, u32 flags, u32 *id);
|
||
|
|
int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
|
||
|
|
void msm_submitqueue_close(struct msm_file_private *ctx);
|
||
|
|
|
||
|
|
void msm_submitqueue_destroy(struct kref *kref);
|
||
|
|
|
||
|
|
|
||
|
|
#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
|
||
|
|
#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
|
||
|
|
|
||
|
|
static inline int align_pitch(int width, int bpp)
|
||
|
|
{
|
||
|
|
int bytespp = (bpp + 7) / 8;
|
||
|
|
/* adreno needs pitch aligned to 32 pixels: */
|
||
|
|
return bytespp * ALIGN(width, 32);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* for the generated headers: */
|
||
|
|
#define INVALID_IDX(idx) ({BUG(); 0;})
|
||
|
|
#define fui(x) ({BUG(); 0;})
|
||
|
|
#define util_float_to_half(x) ({BUG(); 0;})
|
||
|
|
|
||
|
|
|
||
|
|
#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
|
||
|
|
|
||
|
|
/* for conditionally setting boolean flag(s): */
|
||
|
|
#define COND(bool, val) ((bool) ? (val) : 0)
|
||
|
|
|
||
|
|
static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
|
||
|
|
{
|
||
|
|
ktime_t now = ktime_get();
|
||
|
|
unsigned long remaining_jiffies;
|
||
|
|
|
||
|
|
if (ktime_compare(*timeout, now) < 0) {
|
||
|
|
remaining_jiffies = 0;
|
||
|
|
} else {
|
||
|
|
ktime_t rem = ktime_sub(*timeout, now);
|
||
|
|
struct timespec ts = ktime_to_timespec(rem);
|
||
|
|
remaining_jiffies = timespec_to_jiffies(&ts);
|
||
|
|
}
|
||
|
|
|
||
|
|
return remaining_jiffies;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __MSM_DRV_H__ */
|