249 lines
5.6 KiB
C
249 lines
5.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: JB Tsai <jb.tsai@mediatek.com>
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*/
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#ifndef __EDMA_IOCTL_H__
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#define __EDMA_IOCTL_H__
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#define EDMA_EXT_MODE_SIZE 0x40
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#define EDMA_MAGICNO 'v'
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#define EDMA_IOCTL_ENQUE_NORMAL _IOWR(EDMA_MAGICNO, 0,\
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struct edma_normal)
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#define EDMA_IOCTL_ENQUE_FILL _IOWR(EDMA_MAGICNO, 1,\
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struct edma_fill)
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#define EDMA_IOCTL_ENQUE_NUMERICAL _IOWR(EDMA_MAGICNO, 2,\
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struct edma_numerical)
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#define EDMA_IOCTL_ENQUE_FORMAT _IOWR(EDMA_MAGICNO, 3,\
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struct edma_format)
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#define EDMA_IOCTL_ENQUE_COMPRESS _IOWR(EDMA_MAGICNO, 4,\
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struct edma_compress)
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#define EDMA_IOCTL_ENQUE_DECOMPRESS _IOWR(EDMA_MAGICNO, 5,\
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struct edma_decompress)
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#define EDMA_IOCTL_ENQUE_RAW _IOWR(EDMA_MAGICNO, 6,\
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struct edma_raw)
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#define EDMA_IOCTL_DEQUE _IOWR(EDMA_MAGICNO, 7,\
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struct edma_cmd_deque)
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#define EDMA_IOCTL_SYNC_NORMAL _IOWR(EDMA_MAGICNO, 8,\
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struct edma_normal)
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#define EDMA_IOCTL_ENQUE_EXT_MODE _IOWR(EDMA_MAGICNO, 9,\
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struct edma_ext)
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#define EDMA_IOCTL_SYNC_EXT_MODE _IOWR(EDMA_MAGICNO, 10,\
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struct edma_ext)
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enum edma_req_status {
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/** 0: EDMA_REQ_STATUS_ENQUEUE */
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EDMA_REQ_STATUS_ENQUEUE,
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/** 1: EDMA_REQ_STATUS_RUN */
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EDMA_REQ_STATUS_RUN,
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/** 2: EDMA_REQ_STATUS_DEQUEUE */
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EDMA_REQ_STATUS_DEQUEUE,
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/** 3: EDMA_REQ_STATUS_TIMEOUT */
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EDMA_REQ_STATUS_TIMEOUT,
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/** 4: EDMA_REQ_STATUS_INVALID */
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EDMA_REQ_STATUS_INVALID,
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/** 5: EDMA_REQ_STATUS_FLUSH */
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EDMA_REQ_STATUS_FLUSH,
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};
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enum edma_desp_format {
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EDMA_FORMAT_FP32 = 1,
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EDMA_FORMAT_FP16,
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EDMA_FORMAT_I8,
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EDMA_FORMAT_YUV420_2_PLANE_8B,
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EDMA_FORMAT_YUV420_2_PLANE_16B,
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EDMA_FORMAT_YUV420_2_PLANE_P010,
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EDMA_FORMAT_YUV420_2_PLANE_MTK420_PACK_10B,
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EDMA_FORMAT_RGB_8B,
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EDMA_FORMAT_ARGB2SET_8B,
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EDMA_FORMAT_ARGB2SET_16B,
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EDMA_FORMAT_ARGB2SET_2101010,
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EDMA_FORMAT_BITSTREAM_YUV420_8B,
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EDMA_FORMAT_BITSTREAM_YUV420_10B,
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EDMA_FORMAT_BITSTREAM_ARGB_8B,
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EDMA_FORMAT_BITSTREAM_ARGB_10B,
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};
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struct edma_normal {
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__u64 cmd_handle;
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__u32 tile_channel;
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__u32 tile_width;
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__u32 tile_height;
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__u32 src_channel_stride;
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__u32 src_width_stride;
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__u32 dst_channel_stride;
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__u32 dst_width_stride;
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__u32 src_addr;
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__u32 dst_addr;
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__u8 buf_iommu_en;
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};
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struct edma_fill {
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__u64 cmd_handle;
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__u32 tile_channel;
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__u32 tile_width;
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__u32 tile_height;
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__u32 dst_channel_stride;
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__u32 dst_width_stride;
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__u32 dst_addr;
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__u32 fill_value;
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__u8 buf_iommu_en;
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};
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struct edma_numerical {
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__u64 cmd_handle;
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__u32 tile_channel;
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__u32 tile_width;
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__u32 tile_height;
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__u32 src_channel_stride;
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__u32 src_width_stride;
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__u32 dst_channel_stride;
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__u32 dst_width_stride;
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__u32 src_addr;
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__u32 dst_addr;
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__u32 range_scale;
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__u32 min_fp32;
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__u8 in_format;
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__u8 out_format;
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};
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struct edma_format {
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__u64 cmd_handle;
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__u32 src_tile_channel;
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__u32 src_tile_width;
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__u32 src_tile_height;
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__u32 src_channel_stride;
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__u32 src_uv_channel_stride;
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__u32 src_width_stride;
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__u32 src_uv_width_stride;
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__u32 dst_tile_channel;
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__u32 dst_tile_width;
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__u32 dst_channel_stride;
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__u32 dst_uv_channel_stride;
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__u32 dst_width_stride;
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__u32 dst_uv_width_stride;
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__u32 src_addr;
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__u32 src_uv_addr;
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__u32 dst_addr;
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__u32 dst_uv_addr;
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__u32 param_a;
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__u8 in_format;
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__u8 out_format;
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};
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struct edma_compress {
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__u64 cmd_handle;
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__u32 src_tile_channel;
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__u32 src_tile_width;
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__u32 src_tile_height;
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__u32 src_channel_stride;
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__u32 src_uv_channel_stride;
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__u32 src_width_stride;
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__u32 src_uv_width_stride;
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__u32 dst_tile_channel;
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__u32 dst_tile_width;
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__u32 dst_channel_stride;
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__u32 dst_uv_channel_stride;
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__u32 dst_width_stride;
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__u32 dst_uv_width_stride;
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__u32 src_addr;
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__u32 src_uv_addr;
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__u32 dst_addr;
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__u32 dst_uv_addr;
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__u32 param_a;
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__u32 param_m;
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__u32 cmprs_src_pxl;
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__u32 cmprs_dst_pxl;
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__u32 src_c_stride_pxl;
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__u32 src_w_stride_pxl;
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__u32 src_c_offset_m1;
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__u32 src_w_offset_m1;
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__u32 dst_c_stride_pxl;
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__u32 dst_w_stride_pxl;
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__u32 dst_c_offset_m1;
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__u32 dst_w_offset_m1;
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__u8 in_format;
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__u8 out_format;
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__u8 yuv2rgb_mat_bypass;
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__u8 rgb2yuv_mat_bypass;
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__u8 yuv2rgb_mat_select;
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__u8 rgb2yuv_mat_select;
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};
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struct edma_decompress {
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__u64 cmd_handle;
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__u32 src_tile_channel;
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__u32 src_tile_width;
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__u32 src_tile_height;
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__u32 src_channel_stride;
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__u32 src_uv_channel_stride;
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__u32 src_width_stride;
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__u32 src_uv_width_stride;
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__u32 dst_tile_channel;
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__u32 dst_tile_width;
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__u32 dst_channel_stride;
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__u32 dst_uv_channel_stride;
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__u32 dst_width_stride;
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__u32 dst_uv_width_stride;
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__u32 src_addr;
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__u32 src_uv_addr;
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__u32 dst_addr;
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__u32 dst_uv_addr;
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__u32 param_a;
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__u32 param_m;
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__u32 cmprs_src_pxl;
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__u32 cmprs_dst_pxl;
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__u32 src_c_stride_pxl;
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__u32 src_w_stride_pxl;
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__u32 src_c_offset_m1;
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__u32 src_w_offset_m1;
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__u32 dst_c_stride_pxl;
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__u32 dst_w_stride_pxl;
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__u32 dst_c_offset_m1;
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__u32 dst_w_offset_m1;
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__u8 in_format;
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__u8 out_format;
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__u8 yuv2rgb_mat_bypass;
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__u8 rgb2yuv_mat_bypass;
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__u8 yuv2rgb_mat_select;
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__u8 rgb2yuv_mat_select;
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};
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struct edma_raw {
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__u64 cmd_handle;
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__u32 src_tile_channel;
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__u32 src_tile_width;
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__u32 src_tile_height;
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__u32 src_channel_stride;
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__u32 src_width_stride;
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__u32 dst_tile_channel;
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__u32 dst_tile_width;
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__u32 dst_channel_stride;
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__u32 dst_width_stride;
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__u32 src_addr;
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__u32 src_uv_addr;
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__u32 dst_addr;
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__u8 plane_num;
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__u8 unpack_shift;
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__u8 bit_num;
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};
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struct edma_ext {
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__u64 cmd_handle;
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__u32 count;
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__u32 reg_addr;
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__u32 fill_value;
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__u8 desp_iommu_en;
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} __attribute__ ((__packed__));
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struct edma_cmd_deque {
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__u64 cmd_handle;
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__s32 cmd_result;
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__u32 cmd_status;
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};
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#endif /* __EDMA_IOCTL_H__ */
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