244 lines
6.2 KiB
C
244 lines
6.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/cdev.h>
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#include <linux/slab.h>
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#include <linux/kthread.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/sched/clock.h>
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#include "edma_driver.h"
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#include "edma_cmd_hnd.h"
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#include "edma_reg.h"
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#include "apusys_power.h"
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#include "edma_dbgfs.h"
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#include "edma_plat_internal.h"
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#include "apusys_dbg.h"
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#define NO_INTERRUPT 0
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#define EDMA_POWEROFF_TIME_DEFAULT 2000
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static void edma_sw_reset(struct edma_sub *edma_sub);
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void print_error_status(struct edma_sub *edma_sub,
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struct edma_request *req)
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{
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u32 status, i, j;
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unsigned int *ext_reg = NULL;
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status = edma_read_reg32(edma_sub->base_addr, APU_EDMA2_ERR_STATUS);
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pr_notice("%s error status %x\n", edma_sub->sub_name,
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status);
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for (i = 0; i < (EDMA_REG_SHOW_RANGE >> 2); i++) {
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status = edma_read_reg32(edma_sub->base_addr, i*4);
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pr_notice("edma error dump register[0x%x] = 0x%x\n",
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i*4, status);
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}
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for (i = (0xC00/4); i < (0xD00/4); i++) {
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status = edma_read_reg32(edma_sub->base_addr, i*4);
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pr_notice("edma error dump register[0x%x] = 0x%x\n",
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i*4, status);
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}
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if (req->ext_reg_addr != 0) {
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ext_reg = (unsigned int *)
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apusys_mem_query_kva(req->ext_reg_addr);
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pr_notice("kva ext_reg = 0x%p, req->ext_count = %d\n",
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ext_reg, req->ext_count);
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if (ext_reg != 0)
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for (i = 0; i < req->ext_count; i++) {
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for (j = 0; j < EDMA_EXT_MODE_SIZE/4; j++)
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pr_notice("descriptor%d [0x%x] = 0x%x\n",
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i, j*4, *(ext_reg + j));
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}
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else
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pr_notice("not support ext_reg dump!!\n");
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}
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edma_sw_reset(edma_sub);
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}
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irqreturn_t edma_isr_handler(int irq, void *edma_sub_info)
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{
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struct edma_sub *edma_sub = (struct edma_sub *)edma_sub_info;
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u32 status;
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u32 desp0_done;
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u32 desp0_intr;
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u32 desp1_done;
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u32 desp1_intr;
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u32 desp2_done;
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u32 desp2_intr;
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u32 desp3_done;
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u32 desp3_intr;
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u32 desp4_done;
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u32 desp4_intr;
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status = edma_read_reg32(edma_sub->base_addr, APU_EDMA2_INT_STATUS);
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desp0_done = status & DESP0_DONE_STATUS;
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desp1_done = status & DESP1_DONE_STATUS;
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desp2_done = status & DESP2_DONE_STATUS;
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desp3_done = status & DESP3_DONE_STATUS;
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desp4_done = status & EXT_DESP_DONE_STATUS;
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desp0_intr = status & DESP0_DONE_INT_STATUS;
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desp1_intr = status & DESP1_DONE_INT_STATUS;
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desp2_intr = status & DESP2_DONE_INT_STATUS;
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desp3_intr = status & DESP3_DONE_INT_STATUS;
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desp4_intr = status & EXT_DESP_DONE_INT_STATUS;
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edma_sub->is_cmd_done = true;
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if (desp0_done | desp1_done | desp2_done | desp3_done | desp4_done)
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wake_up_interruptible(&edma_sub->cmd_wait);
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if (desp0_intr)
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_INT_STATUS,
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DESP0_DONE_INT_STATUS);
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else if (desp1_intr)
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_INT_STATUS,
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DESP1_DONE_INT_STATUS);
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else if (desp2_intr)
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_INT_STATUS,
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DESP2_DONE_INT_STATUS);
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else if (desp3_intr)
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_INT_STATUS,
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DESP3_DONE_INT_STATUS);
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else if (desp4_intr)
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_INT_STATUS,
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EXT_DESP_DONE_INT_STATUS);
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return IRQ_HANDLED;
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}
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void edma_enable_sequence(struct edma_sub *edma_sub)
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{
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, CLK_ENABLE);
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, DMA_SW_RST);
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edma_clear_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, DMA_SW_RST);
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}
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static void edma_sw_reset(struct edma_sub *edma_sub)
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{
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u32 value = 0, count = 0;
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unsigned long flags;
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LOG_DBG("%s\n", __func__);
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spin_lock_irqsave(&edma_sub->reg_lock, flags);
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, CLK_ENABLE);
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, AXI_PROT_EN);
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while (!(value & RST_PROT_IDLE)) {
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value = edma_read_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0);
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udelay(5);
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count++;
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if (count > 10000) {
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u32 status, i;
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spin_unlock_irqrestore(&edma_sub->reg_lock, flags);
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/* dump error log */
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pr_notice("hang on %s direct dump...\n", __func__);
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for (i = 0; i < (EDMA_REG_SHOW_RANGE >> 2); i++) {
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status = edma_read_reg32(edma_sub->base_addr,
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i*4);
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pr_notice("hang %s edma error dump [0x%x] = 0x%x\n",
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__func__, i*4, status);
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}
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apusys_reg_dump();
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/* continues do edma */
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spin_lock_irqsave(&edma_sub->reg_lock, flags);
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break;
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}
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}
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LOG_DBG("value = 0x%x\n", value);
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edma_set_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, DMA_SW_RST);
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udelay(5);
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edma_clear_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, DMA_SW_RST);
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udelay(5);
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edma_clear_reg32(edma_sub->base_addr, APU_EDMA2_CTL_0, AXI_PROT_EN);
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spin_unlock_irqrestore(&edma_sub->reg_lock, flags);
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}
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/**
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* @brief trigger edma external mode
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* parameters:
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* base_addr: each edma base address
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* ext_addr: external descriptor mem addr
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* num_desp: number of desc.
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* desp_iommu_en: enable iommu or not
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*/
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void edma_trigger_external(void __iomem *base_addr, u32 ext_addr, u32 num_desp,
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u8 desp_iommu_en)
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{
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edma_set_reg32(base_addr, APU_EDMA2_CTL_0, EDMA_DESCRIPTOR_MODE);
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num_desp--;
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if (desp_iommu_en)
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edma_write_reg32(base_addr, APU_EDMA2_EXT_DESP_CFG_0,
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EXT_DESP_INT_ENABLE | EXT_DESP_USER_IOMMU | num_desp);
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else
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edma_write_reg32(base_addr, APU_EDMA2_EXT_DESP_CFG_0,
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EXT_DESP_INT_ENABLE | num_desp);
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edma_write_reg32(base_addr, APU_EDMA2_EXT_DESP_CFG_1, ext_addr);
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edma_set_reg32(base_addr, APU_EDMA2_CFG_0, EXT_DESP_START);
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}
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/**
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* @brief excute request by each edma_sub
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* parameters:
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* edma_sub: include each edma base address
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*/
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int edma_exe_v20(struct edma_sub *edma_sub, struct edma_request *req)
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{
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int ret = 0;
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void __iomem *base_addr;
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unsigned long flags;
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base_addr = edma_sub->base_addr;
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//edma_enable_sequence(edma_sub);
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edma_sw_reset(edma_sub); // no need in edma 3.0
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spin_lock_irqsave(&edma_sub->reg_lock, flags);
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edma_write_reg32(base_addr, APU_EDMA2_FILL_VALUE, req->fill_value);
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edma_trigger_external(edma_sub->base_addr,
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req->ext_reg_addr,
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req->ext_count,
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req->desp_iommu_en);
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spin_unlock_irqrestore(&edma_sub->reg_lock, flags);
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return ret;
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}
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