334 lines
12 KiB
C
334 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Header Parser definitions for Marvell PPv2 Network Controller
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*
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* Copyright (C) 2014 Marvell
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*
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* Marcin Wojtas <mw@semihalf.com>
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*/
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#ifndef _MVPP2_PRS_H_
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#define _MVPP2_PRS_H_
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include "mvpp2.h"
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/* Parser constants */
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#define MVPP2_PRS_TCAM_SRAM_SIZE 256
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#define MVPP2_PRS_TCAM_WORDS 6
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#define MVPP2_PRS_SRAM_WORDS 4
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#define MVPP2_PRS_FLOW_ID_SIZE 64
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#define MVPP2_PRS_FLOW_ID_MASK 0x3f
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#define MVPP2_PRS_TCAM_ENTRY_INVALID 1
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#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
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#define MVPP2_PRS_IPV4_HEAD 0x40
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#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
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#define MVPP2_PRS_IPV4_MC 0xe0
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#define MVPP2_PRS_IPV4_MC_MASK 0xf0
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#define MVPP2_PRS_IPV4_BC_MASK 0xff
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#define MVPP2_PRS_IPV4_IHL 0x5
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#define MVPP2_PRS_IPV4_IHL_MASK 0xf
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#define MVPP2_PRS_IPV6_MC 0xff
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#define MVPP2_PRS_IPV6_MC_MASK 0xff
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#define MVPP2_PRS_IPV6_HOP_MASK 0xff
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#define MVPP2_PRS_TCAM_PROTO_MASK 0xff
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#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
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#define MVPP2_PRS_DBL_VLANS_MAX 100
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#define MVPP2_PRS_CAST_MASK BIT(0)
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#define MVPP2_PRS_MCAST_VAL BIT(0)
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#define MVPP2_PRS_UCAST_VAL 0x0
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/* Tcam structure:
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* - lookup ID - 4 bits
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* - port ID - 1 byte
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* - additional information - 1 byte
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* - header data - 8 bytes
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* The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
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*/
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#define MVPP2_PRS_AI_BITS 8
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#define MVPP2_PRS_AI_MASK 0xff
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#define MVPP2_PRS_PORT_MASK 0xff
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#define MVPP2_PRS_LU_MASK 0xf
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/* TCAM entries in registers are accessed using 16 data bits + 16 enable bits */
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#define MVPP2_PRS_BYTE_TO_WORD(byte) ((byte) / 2)
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#define MVPP2_PRS_BYTE_IN_WORD(byte) ((byte) % 2)
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#define MVPP2_PRS_TCAM_EN(data) ((data) << 16)
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#define MVPP2_PRS_TCAM_AI_WORD 4
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#define MVPP2_PRS_TCAM_AI(ai) (ai)
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#define MVPP2_PRS_TCAM_AI_EN(ai) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_AI(ai))
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#define MVPP2_PRS_TCAM_PORT_WORD 4
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#define MVPP2_PRS_TCAM_PORT(p) ((p) << 8)
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#define MVPP2_PRS_TCAM_PORT_EN(p) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_PORT(p))
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#define MVPP2_PRS_TCAM_LU_WORD 5
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#define MVPP2_PRS_TCAM_LU(lu) (lu)
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#define MVPP2_PRS_TCAM_LU_EN(lu) MVPP2_PRS_TCAM_EN(MVPP2_PRS_TCAM_LU(lu))
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#define MVPP2_PRS_TCAM_INV_WORD 5
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#define MVPP2_PRS_VID_TCAM_BYTE 2
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/* TCAM range for unicast and multicast filtering. We have 25 entries per port,
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* with 4 dedicated to UC filtering and the rest to multicast filtering.
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* Additionnally we reserve one entry for the broadcast address, and one for
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* each port's own address.
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*/
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#define MVPP2_PRS_MAC_UC_MC_FILT_MAX 25
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#define MVPP2_PRS_MAC_RANGE_SIZE 80
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/* Number of entries per port dedicated to UC and MC filtering */
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#define MVPP2_PRS_MAC_UC_FILT_MAX 4
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#define MVPP2_PRS_MAC_MC_FILT_MAX (MVPP2_PRS_MAC_UC_MC_FILT_MAX - \
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MVPP2_PRS_MAC_UC_FILT_MAX)
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/* There is a TCAM range reserved for VLAN filtering entries, range size is 33
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* 10 VLAN ID filter entries per port
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* 1 default VLAN filter entry per port
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* It is assumed that there are 3 ports for filter, not including loopback port
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*/
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#define MVPP2_PRS_VLAN_FILT_MAX 11
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#define MVPP2_PRS_VLAN_FILT_RANGE_SIZE 33
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#define MVPP2_PRS_VLAN_FILT_MAX_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 2)
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#define MVPP2_PRS_VLAN_FILT_DFLT_ENTRY (MVPP2_PRS_VLAN_FILT_MAX - 1)
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/* Tcam entries ID */
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#define MVPP2_PE_DROP_ALL 0
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#define MVPP2_PE_FIRST_FREE_TID 1
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/* MAC filtering range */
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#define MVPP2_PE_MAC_RANGE_END (MVPP2_PE_VID_FILT_RANGE_START - 1)
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#define MVPP2_PE_MAC_RANGE_START (MVPP2_PE_MAC_RANGE_END - \
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MVPP2_PRS_MAC_RANGE_SIZE + 1)
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/* VLAN filtering range */
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#define MVPP2_PE_VID_FILT_RANGE_END (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
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#define MVPP2_PE_VID_FILT_RANGE_START (MVPP2_PE_VID_FILT_RANGE_END - \
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MVPP2_PRS_VLAN_FILT_RANGE_SIZE + 1)
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#define MVPP2_PE_LAST_FREE_TID (MVPP2_PE_MAC_RANGE_START - 1)
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#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
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#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
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#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
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#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
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#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 22)
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#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 21)
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#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 20)
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#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
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#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
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#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
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#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
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#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
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#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
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#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
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#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
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#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
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#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
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#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
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#define MVPP2_PE_VID_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
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#define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
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#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
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#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
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#define MVPP2_PE_FC_DROP (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
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#define MVPP2_PE_MAC_MC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
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#define MVPP2_PE_MAC_UC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
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#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
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#define MVPP2_PRS_VID_PORT_FIRST(port) (MVPP2_PE_VID_FILT_RANGE_START + \
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((port) * MVPP2_PRS_VLAN_FILT_MAX))
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#define MVPP2_PRS_VID_PORT_LAST(port) (MVPP2_PRS_VID_PORT_FIRST(port) \
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+ MVPP2_PRS_VLAN_FILT_MAX_ENTRY)
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/* Index of default vid filter for given port */
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#define MVPP2_PRS_VID_PORT_DFLT(port) (MVPP2_PRS_VID_PORT_FIRST(port) \
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+ MVPP2_PRS_VLAN_FILT_DFLT_ENTRY)
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/* Sram structure
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* The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
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*/
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#define MVPP2_PRS_SRAM_RI_OFFS 0
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#define MVPP2_PRS_SRAM_RI_WORD 0
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#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
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#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
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#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
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#define MVPP2_PRS_SRAM_SHIFT_OFFS 64
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#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
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#define MVPP2_PRS_SRAM_SHIFT_MASK 0xff
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#define MVPP2_PRS_SRAM_UDF_OFFS 73
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#define MVPP2_PRS_SRAM_UDF_BITS 8
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#define MVPP2_PRS_SRAM_UDF_MASK 0xff
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#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
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#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
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#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
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#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
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#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
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#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
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#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
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#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
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#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
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#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
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#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
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#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
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#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
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#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
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#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
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#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
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#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
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#define MVPP2_PRS_SRAM_AI_OFFS 90
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#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
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#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
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#define MVPP2_PRS_SRAM_AI_MASK 0xff
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#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
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#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
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#define MVPP2_PRS_SRAM_LU_DONE_BIT 110
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#define MVPP2_PRS_SRAM_LU_GEN_BIT 111
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/* Sram result info bits assignment */
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#define MVPP2_PRS_RI_MAC_ME_MASK 0x1
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#define MVPP2_PRS_RI_DSA_MASK 0x2
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#define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
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#define MVPP2_PRS_RI_VLAN_NONE 0x0
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#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
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#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
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#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
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#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
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#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
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#define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
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#define MVPP2_PRS_RI_L2_UCAST 0x0
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#define MVPP2_PRS_RI_L2_MCAST BIT(9)
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#define MVPP2_PRS_RI_L2_BCAST BIT(10)
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#define MVPP2_PRS_RI_PPPOE_MASK 0x800
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#define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
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#define MVPP2_PRS_RI_L3_UN 0x0
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#define MVPP2_PRS_RI_L3_IP4 BIT(12)
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#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
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#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
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#define MVPP2_PRS_RI_L3_IP6 BIT(14)
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#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
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#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
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#define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
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#define MVPP2_PRS_RI_L3_UCAST 0x0
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#define MVPP2_PRS_RI_L3_MCAST BIT(15)
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#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
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#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
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#define MVPP2_PRS_RI_IP_FRAG_TRUE BIT(17)
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#define MVPP2_PRS_RI_UDF3_MASK 0x300000
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#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
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#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
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#define MVPP2_PRS_RI_L4_TCP BIT(22)
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#define MVPP2_PRS_RI_L4_UDP BIT(23)
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#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
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#define MVPP2_PRS_RI_UDF7_MASK 0x60000000
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#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
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#define MVPP2_PRS_RI_DROP_MASK 0x80000000
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#define MVPP2_PRS_IP_MASK (MVPP2_PRS_RI_L3_PROTO_MASK | \
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MVPP2_PRS_RI_IP_FRAG_MASK | \
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MVPP2_PRS_RI_L4_PROTO_MASK)
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/* Sram additional info bits assignment */
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#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
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#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
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#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
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#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
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#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
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#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
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#define MVPP2_PRS_SINGLE_VLAN_AI 0
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#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
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#define MVPP2_PRS_EDSA_VID_AI_BIT BIT(0)
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/* DSA/EDSA type */
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#define MVPP2_PRS_TAGGED true
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#define MVPP2_PRS_UNTAGGED false
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#define MVPP2_PRS_EDSA true
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#define MVPP2_PRS_DSA false
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/* MAC entries, shadow udf */
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enum mvpp2_prs_udf {
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MVPP2_PRS_UDF_MAC_DEF,
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MVPP2_PRS_UDF_MAC_RANGE,
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MVPP2_PRS_UDF_L2_DEF,
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MVPP2_PRS_UDF_L2_DEF_COPY,
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MVPP2_PRS_UDF_L2_USER,
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};
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/* Lookup ID */
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enum mvpp2_prs_lookup {
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MVPP2_PRS_LU_MH,
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|
MVPP2_PRS_LU_MAC,
|
||
|
|
MVPP2_PRS_LU_DSA,
|
||
|
|
MVPP2_PRS_LU_VLAN,
|
||
|
|
MVPP2_PRS_LU_VID,
|
||
|
|
MVPP2_PRS_LU_L2,
|
||
|
|
MVPP2_PRS_LU_PPPOE,
|
||
|
|
MVPP2_PRS_LU_IP4,
|
||
|
|
MVPP2_PRS_LU_IP6,
|
||
|
|
MVPP2_PRS_LU_FLOWS,
|
||
|
|
MVPP2_PRS_LU_LAST,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mvpp2_prs_entry {
|
||
|
|
u32 index;
|
||
|
|
u32 tcam[MVPP2_PRS_TCAM_WORDS];
|
||
|
|
u32 sram[MVPP2_PRS_SRAM_WORDS];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mvpp2_prs_result_info {
|
||
|
|
u32 ri;
|
||
|
|
u32 ri_mask;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mvpp2_prs_shadow {
|
||
|
|
bool valid;
|
||
|
|
bool finish;
|
||
|
|
|
||
|
|
/* Lookup ID */
|
||
|
|
int lu;
|
||
|
|
|
||
|
|
/* User defined offset */
|
||
|
|
int udf;
|
||
|
|
|
||
|
|
/* Result info */
|
||
|
|
u32 ri;
|
||
|
|
u32 ri_mask;
|
||
|
|
};
|
||
|
|
|
||
|
|
int mvpp2_prs_default_init(struct platform_device *pdev, struct mvpp2 *priv);
|
||
|
|
|
||
|
|
int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe,
|
||
|
|
int tid);
|
||
|
|
|
||
|
|
unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe);
|
||
|
|
|
||
|
|
void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
|
||
|
|
unsigned int offs, unsigned char *byte,
|
||
|
|
unsigned char *enable);
|
||
|
|
|
||
|
|
int mvpp2_prs_mac_da_accept(struct mvpp2_port *port, const u8 *da, bool add);
|
||
|
|
|
||
|
|
int mvpp2_prs_tag_mode_set(struct mvpp2 *priv, int port, int type);
|
||
|
|
|
||
|
|
int mvpp2_prs_add_flow(struct mvpp2 *priv, int flow, u32 ri, u32 ri_mask);
|
||
|
|
|
||
|
|
int mvpp2_prs_def_flow(struct mvpp2_port *port);
|
||
|
|
|
||
|
|
void mvpp2_prs_vid_enable_filtering(struct mvpp2_port *port);
|
||
|
|
|
||
|
|
void mvpp2_prs_vid_disable_filtering(struct mvpp2_port *port);
|
||
|
|
|
||
|
|
int mvpp2_prs_vid_entry_add(struct mvpp2_port *port, u16 vid);
|
||
|
|
|
||
|
|
void mvpp2_prs_vid_entry_remove(struct mvpp2_port *port, u16 vid);
|
||
|
|
|
||
|
|
void mvpp2_prs_vid_remove_all(struct mvpp2_port *port);
|
||
|
|
|
||
|
|
void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port,
|
||
|
|
enum mvpp2_prs_l2_cast l2_cast, bool add);
|
||
|
|
|
||
|
|
void mvpp2_prs_mac_del_all(struct mvpp2_port *port);
|
||
|
|
|
||
|
|
int mvpp2_prs_update_mac_da(struct net_device *dev, const u8 *da);
|
||
|
|
|
||
|
|
int mvpp2_prs_hits(struct mvpp2 *priv, int index);
|
||
|
|
|
||
|
|
#endif
|