226 lines
6.3 KiB
C
226 lines
6.3 KiB
C
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/*
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* TI Common Platform Time Sync
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*
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* Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _TI_CPTS_H_
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#define _TI_CPTS_H_
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#if IS_ENABLED(CONFIG_TI_CPTS)
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clocksource.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/skbuff.h>
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#include <linux/ptp_classify.h>
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#include <linux/timecounter.h>
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struct cpsw_cpts {
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u32 idver; /* Identification and version */
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u32 control; /* Time sync control */
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u32 res1;
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u32 ts_push; /* Time stamp event push */
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u32 ts_load_val; /* Time stamp load value */
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u32 ts_load_en; /* Time stamp load enable */
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u32 res2[2];
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u32 intstat_raw; /* Time sync interrupt status raw */
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u32 intstat_masked; /* Time sync interrupt status masked */
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u32 int_enable; /* Time sync interrupt enable */
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u32 res3;
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u32 event_pop; /* Event interrupt pop */
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u32 event_low; /* 32 Bit Event Time Stamp */
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u32 event_high; /* Event Type Fields */
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};
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/* Bit definitions for the IDVER register */
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#define TX_IDENT_SHIFT (16) /* TX Identification Value */
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#define TX_IDENT_MASK (0xffff)
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#define RTL_VER_SHIFT (11) /* RTL Version Value */
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#define RTL_VER_MASK (0x1f)
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#define MAJOR_VER_SHIFT (8) /* Major Version Value */
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#define MAJOR_VER_MASK (0x7)
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#define MINOR_VER_SHIFT (0) /* Minor Version Value */
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#define MINOR_VER_MASK (0xff)
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/* Bit definitions for the CONTROL register */
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#define HW4_TS_PUSH_EN (1<<11) /* Hardware push 4 enable */
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#define HW3_TS_PUSH_EN (1<<10) /* Hardware push 3 enable */
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#define HW2_TS_PUSH_EN (1<<9) /* Hardware push 2 enable */
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#define HW1_TS_PUSH_EN (1<<8) /* Hardware push 1 enable */
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#define INT_TEST (1<<1) /* Interrupt Test */
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#define CPTS_EN (1<<0) /* Time Sync Enable */
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/*
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* Definitions for the single bit resisters:
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* TS_PUSH TS_LOAD_EN INTSTAT_RAW INTSTAT_MASKED INT_ENABLE EVENT_POP
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*/
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#define TS_PUSH (1<<0) /* Time stamp event push */
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#define TS_LOAD_EN (1<<0) /* Time Stamp Load */
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#define TS_PEND_RAW (1<<0) /* int read (before enable) */
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#define TS_PEND (1<<0) /* masked interrupt read (after enable) */
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#define TS_PEND_EN (1<<0) /* masked interrupt enable */
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#define EVENT_POP (1<<0) /* writing discards one event */
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/* Bit definitions for the EVENT_HIGH register */
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#define PORT_NUMBER_SHIFT (24) /* Indicates Ethernet port or HW pin */
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#define PORT_NUMBER_MASK (0x1f)
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#define EVENT_TYPE_SHIFT (20) /* Time sync event type */
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#define EVENT_TYPE_MASK (0xf)
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#define MESSAGE_TYPE_SHIFT (16) /* PTP message type */
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#define MESSAGE_TYPE_MASK (0xf)
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#define SEQUENCE_ID_SHIFT (0) /* PTP message sequence ID */
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#define SEQUENCE_ID_MASK (0xffff)
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enum {
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CPTS_EV_PUSH, /* Time Stamp Push Event */
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CPTS_EV_ROLL, /* Time Stamp Rollover Event */
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CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
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CPTS_EV_HW, /* Hardware Time Stamp Push Event */
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CPTS_EV_RX, /* Ethernet Receive Event */
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CPTS_EV_TX, /* Ethernet Transmit Event */
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};
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#define CPTS_FIFO_DEPTH 16
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#define CPTS_MAX_EVENTS 32
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struct cpts_event {
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struct list_head list;
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unsigned long tmo;
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u32 high;
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u32 low;
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};
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struct cpts {
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struct device *dev;
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struct cpsw_cpts __iomem *reg;
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int tx_enable;
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int rx_enable;
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struct ptp_clock_info info;
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struct ptp_clock *clock;
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spinlock_t lock; /* protects time registers */
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u32 cc_mult; /* for the nominal frequency */
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struct cyclecounter cc;
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struct timecounter tc;
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int phc_index;
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struct clk *refclk;
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struct list_head events;
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struct list_head pool;
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struct cpts_event pool_data[CPTS_MAX_EVENTS];
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unsigned long ov_check_period;
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struct sk_buff_head txq;
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};
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void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb);
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void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb);
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int cpts_register(struct cpts *cpts);
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void cpts_unregister(struct cpts *cpts);
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struct cpts *cpts_create(struct device *dev, void __iomem *regs,
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struct device_node *node);
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void cpts_release(struct cpts *cpts);
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static inline void cpts_rx_enable(struct cpts *cpts, int enable)
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{
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cpts->rx_enable = enable;
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}
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static inline bool cpts_is_rx_enabled(struct cpts *cpts)
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{
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return !!cpts->rx_enable;
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}
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static inline void cpts_tx_enable(struct cpts *cpts, int enable)
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{
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cpts->tx_enable = enable;
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}
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static inline bool cpts_is_tx_enabled(struct cpts *cpts)
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{
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return !!cpts->tx_enable;
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}
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static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
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{
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unsigned int class = ptp_classify_raw(skb);
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if (class == PTP_CLASS_NONE)
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return false;
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return true;
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}
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#else
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struct cpts;
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static inline void cpts_rx_timestamp(struct cpts *cpts, struct sk_buff *skb)
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{
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}
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static inline void cpts_tx_timestamp(struct cpts *cpts, struct sk_buff *skb)
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{
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}
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static inline
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struct cpts *cpts_create(struct device *dev, void __iomem *regs,
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struct device_node *node)
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{
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return NULL;
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}
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static inline void cpts_release(struct cpts *cpts)
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{
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}
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static inline int
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cpts_register(struct cpts *cpts)
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{
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return 0;
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}
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static inline void cpts_unregister(struct cpts *cpts)
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{
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}
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static inline void cpts_rx_enable(struct cpts *cpts, int enable)
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{
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}
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static inline bool cpts_is_rx_enabled(struct cpts *cpts)
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{
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return false;
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}
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static inline void cpts_tx_enable(struct cpts *cpts, int enable)
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{
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}
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static inline bool cpts_is_tx_enabled(struct cpts *cpts)
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{
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return false;
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}
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static inline bool cpts_can_timestamp(struct cpts *cpts, struct sk_buff *skb)
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{
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return false;
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}
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#endif
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#endif
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