378 lines
12 KiB
C
378 lines
12 KiB
C
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/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Intel Deutschland GmbH
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* Copyright(c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#include "iwl-trans.h"
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#include "iwl-prph.h"
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#include "iwl-context-info.h"
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#include "iwl-context-info-gen3.h"
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#include "internal.h"
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/*
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* Start up NIC's basic functionality after it has been reset
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* (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
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* NOTE: This does not load uCode nor start the embedded processor
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*/
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static int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
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{
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int ret = 0;
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IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
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/*
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* Use "set_bit" below rather than "write", to preserve any hardware
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* bits already set by default after reset.
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*/
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/*
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* Disable L0s without affecting L1;
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* don't wait for ICH L0s (ICH bug W/A)
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*/
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iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
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CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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/* Set FH wait threshold to maximum (HW error during stress W/A) */
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iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
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/*
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* Enable HAP INTA (interrupt from management bus) to
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* wake device's PCI Express link L1a -> L0s
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*/
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
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iwl_pcie_apm_config(trans);
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/*
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* Set "initialization complete" bit to move adapter from
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* D0U* --> D0A* (powered-up active) state.
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*/
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iwl_set_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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/*
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* Wait for clock stabilization; once stabilized, access to
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* device-internal resources is supported, e.g. iwl_write_prph()
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* and accesses to uCode SRAM.
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*/
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ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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BIT(trans->cfg->csr->flag_mac_clock_ready),
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25000);
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if (ret < 0) {
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IWL_DEBUG_INFO(trans, "Failed to init the card\n");
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return ret;
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}
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set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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return 0;
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}
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static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
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{
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IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
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if (op_mode_leave) {
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if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
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iwl_pcie_gen2_apm_init(trans);
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/* inform ME that we are leaving */
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iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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CSR_RESET_LINK_PWR_MGMT_DISABLED);
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iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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CSR_HW_IF_CONFIG_REG_PREPARE |
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CSR_HW_IF_CONFIG_REG_ENABLE_PME);
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mdelay(1);
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iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
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CSR_RESET_LINK_PWR_MGMT_DISABLED);
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mdelay(5);
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}
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clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
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/* Stop device's DMA activity */
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iwl_pcie_apm_stop_master(trans);
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iwl_trans_sw_reset(trans);
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/*
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* Clear "initialization complete" bit to move adapter from
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* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
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*/
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_init_done));
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}
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void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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lockdep_assert_held(&trans_pcie->mutex);
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if (trans_pcie->is_down)
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return;
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trans_pcie->is_down = true;
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/* Stop dbgc before stopping device */
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iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
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udelay(100);
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iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
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/* tell the device to stop sending interrupts */
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iwl_disable_interrupts(trans);
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/* device going down, Stop using ICT table */
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iwl_pcie_disable_ict(trans);
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/*
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* If a HW restart happens during firmware loading,
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* then the firmware loading might call this function
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* and later it might be called again due to the
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* restart. So don't process again if the device is
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* already dead.
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*/
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if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
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IWL_DEBUG_INFO(trans,
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"DEVICE_ENABLED bit was set and is now cleared\n");
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iwl_pcie_gen2_tx_stop(trans);
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iwl_pcie_rx_stop(trans);
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}
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iwl_pcie_ctxt_info_free_paging(trans);
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if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560)
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iwl_pcie_ctxt_info_gen3_free(trans);
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else
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iwl_pcie_ctxt_info_free(trans);
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/* Make sure (redundant) we've released our request to stay awake */
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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BIT(trans->cfg->csr->flag_mac_access_req));
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/* Stop the device, and put it in low power state */
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iwl_pcie_gen2_apm_stop(trans, false);
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iwl_trans_sw_reset(trans);
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/*
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* Upon stop, the IVAR table gets erased, so msi-x won't
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* work. This causes a bug in RF-KILL flows, since the interrupt
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* that enables radio won't fire on the correct irq, and the
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* driver won't be able to handle the interrupt.
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* Configure the IVAR table again after reset.
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*/
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iwl_pcie_conf_msix_hw(trans_pcie);
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/*
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* Upon stop, the APM issues an interrupt if HW RF kill is set.
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* This is a bug in certain verions of the hardware.
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* Certain devices also keep sending HW RF kill interrupt all
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* the time, unless the interrupt is ACKed even if the interrupt
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* should be masked. Re-ACK all the interrupts here.
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*/
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iwl_disable_interrupts(trans);
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/* clear all status bits */
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clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
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clear_bit(STATUS_INT_ENABLED, &trans->status);
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clear_bit(STATUS_TPOWER_PMI, &trans->status);
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/*
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* Even if we stop the HW, we still want the RF kill
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* interrupt
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*/
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iwl_enable_rfkill_int(trans);
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/* re-take ownership to prevent other users from stealing the device */
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iwl_pcie_prepare_card_hw(trans);
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}
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void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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bool was_in_rfkill;
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mutex_lock(&trans_pcie->mutex);
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trans_pcie->opmode_down = true;
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was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
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_iwl_trans_pcie_gen2_stop_device(trans, low_power);
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iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
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mutex_unlock(&trans_pcie->mutex);
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}
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static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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/* TODO: most of the logic can be removed in A0 - but not in Z0 */
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spin_lock(&trans_pcie->irq_lock);
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iwl_pcie_gen2_apm_init(trans);
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spin_unlock(&trans_pcie->irq_lock);
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iwl_op_mode_nic_config(trans->op_mode);
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/* Allocate the RX queue, or reset if it is already allocated */
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if (iwl_pcie_gen2_rx_init(trans))
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return -ENOMEM;
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/* Allocate or reset and init all Tx and Command queues */
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if (iwl_pcie_gen2_tx_init(trans))
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return -ENOMEM;
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/* enable shadow regs in HW */
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iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
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IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
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return 0;
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}
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void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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iwl_pcie_reset_ict(trans);
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/* make sure all queue are not stopped/used */
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memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
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memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
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/* now that we got alive we can free the fw image & the context info.
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* paging memory cannot be freed included since FW will still use it
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*/
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iwl_pcie_ctxt_info_free(trans);
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/*
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* Re-enable all the interrupts, including the RF-Kill one, now that
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* the firmware is alive.
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*/
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iwl_enable_interrupts(trans);
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mutex_lock(&trans_pcie->mutex);
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iwl_pcie_check_hw_rf_kill(trans);
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mutex_unlock(&trans_pcie->mutex);
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}
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int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
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const struct fw_img *fw, bool run_in_rfkill)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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bool hw_rfkill;
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int ret;
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/* This may fail if AMT took ownership of the device */
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if (iwl_pcie_prepare_card_hw(trans)) {
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IWL_WARN(trans, "Exit HW not ready\n");
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ret = -EIO;
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goto out;
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}
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iwl_enable_rfkill_int(trans);
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iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
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/*
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* We enabled the RF-Kill interrupt and the handler may very
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* well be running. Disable the interrupts to make sure no other
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* interrupt can be fired.
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*/
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iwl_disable_interrupts(trans);
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/* Make sure it finished running */
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iwl_pcie_synchronize_irqs(trans);
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mutex_lock(&trans_pcie->mutex);
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/* If platform's RF_KILL switch is NOT set to KILL */
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hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
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if (hw_rfkill && !run_in_rfkill) {
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ret = -ERFKILL;
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goto out;
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}
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/* Someone called stop_device, don't try to start_fw */
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if (trans_pcie->is_down) {
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IWL_WARN(trans,
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"Can't start_fw since the HW hasn't been started\n");
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ret = -EIO;
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goto out;
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}
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/* make sure rfkill handshake bits are cleared */
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
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iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
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|
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CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
|
||
|
|
|
||
|
|
/* clear (again), then enable host interrupts */
|
||
|
|
iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
|
||
|
|
|
||
|
|
ret = iwl_pcie_gen2_nic_init(trans);
|
||
|
|
if (ret) {
|
||
|
|
IWL_ERR(trans, "Unable to init nic\n");
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560)
|
||
|
|
ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
|
||
|
|
else
|
||
|
|
ret = iwl_pcie_ctxt_info_init(trans, fw);
|
||
|
|
if (ret)
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
/* re-check RF-Kill state since we may have missed the interrupt */
|
||
|
|
hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
|
||
|
|
if (hw_rfkill && !run_in_rfkill)
|
||
|
|
ret = -ERFKILL;
|
||
|
|
|
||
|
|
out:
|
||
|
|
mutex_unlock(&trans_pcie->mutex);
|
||
|
|
return ret;
|
||
|
|
}
|