68 lines
2.2 KiB
Plaintext
68 lines
2.2 KiB
Plaintext
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menuconfig FSL_DPAA
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bool "QorIQ DPAA1 framework support"
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depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
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select GENERIC_ALLOCATOR
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help
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The Freescale Data Path Acceleration Architecture (DPAA) is a set of
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hardware components on specific QorIQ multicore processors.
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This architecture provides the infrastructure to support simplified
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sharing of networking interfaces and accelerators by multiple CPUs.
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The major h/w blocks composing DPAA are BMan and QMan.
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The Buffer Manager (BMan) is a hardware buffer pool management block
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that allows software and accelerators on the datapath to acquire and
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release buffers in order to build frames.
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The Queue Manager (QMan) is a hardware queue management block
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that allows software and accelerators on the datapath to enqueue and
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dequeue frames in order to communicate.
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if FSL_DPAA
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config FSL_DPAA_CHECKING
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bool "Additional driver checking"
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help
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Compiles in additional checks, to sanity-check the drivers and
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any use of the exported API. Not recommended for performance.
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config FSL_BMAN_TEST
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tristate "BMan self-tests"
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help
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Compile the BMan self-test code. These tests will
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exercise the BMan APIs to confirm functionality
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of both the software drivers and hardware device.
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config FSL_BMAN_TEST_API
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bool "High-level API self-test"
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depends on FSL_BMAN_TEST
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default y
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help
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This requires the presence of cpu-affine portals, and performs
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high-level API testing with them (whichever portal(s) are affine
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to the cpu(s) the test executes on).
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config FSL_QMAN_TEST
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tristate "QMan self-tests"
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help
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Compile self-test code for QMan.
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config FSL_QMAN_TEST_API
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bool "QMan high-level self-test"
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depends on FSL_QMAN_TEST
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default y
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help
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This requires the presence of cpu-affine portals, and performs
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high-level API testing with them (whichever portal(s) are affine to
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the cpu(s) the test executes on).
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config FSL_QMAN_TEST_STASH
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bool "QMan 'hot potato' data-stashing self-test"
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depends on FSL_QMAN_TEST
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default y
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help
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This performs a "hot potato" style test enqueuing/dequeuing a frame
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across a series of FQs scheduled to different portals (and cpus), with
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DQRR, data and context stashing always on.
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endif # FSL_DPAA
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