357 lines
8.8 KiB
C
357 lines
8.8 KiB
C
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/*
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* Sonics Silicon Backplane
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* Broadcom MIPS core driver
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*
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* Copyright 2005, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "ssb_private.h"
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#include <linux/ssb/ssb.h>
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#include <linux/mtd/physmap.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <linux/time.h>
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#ifdef CONFIG_BCM47XX
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#include <linux/bcm47xx_nvram.h>
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#endif
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static const char * const part_probes[] = { "bcm47xxpart", NULL };
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static struct physmap_flash_data ssb_pflash_data = {
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.part_probe_types = part_probes,
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};
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static struct resource ssb_pflash_resource = {
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.name = "ssb_pflash",
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.flags = IORESOURCE_MEM,
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};
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struct platform_device ssb_pflash_dev = {
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.name = "physmap-flash",
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.dev = {
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.platform_data = &ssb_pflash_data,
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},
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.resource = &ssb_pflash_resource,
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.num_resources = 1,
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};
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static inline u32 mips_read32(struct ssb_mipscore *mcore,
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u16 offset)
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{
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return ssb_read32(mcore->dev, offset);
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}
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static inline void mips_write32(struct ssb_mipscore *mcore,
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u16 offset,
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u32 value)
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{
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ssb_write32(mcore->dev, offset, value);
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}
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static const u32 ipsflag_irq_mask[] = {
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0,
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SSB_IPSFLAG_IRQ1,
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SSB_IPSFLAG_IRQ2,
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SSB_IPSFLAG_IRQ3,
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SSB_IPSFLAG_IRQ4,
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};
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static const u32 ipsflag_irq_shift[] = {
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0,
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SSB_IPSFLAG_IRQ1_SHIFT,
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SSB_IPSFLAG_IRQ2_SHIFT,
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SSB_IPSFLAG_IRQ3_SHIFT,
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SSB_IPSFLAG_IRQ4_SHIFT,
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};
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static inline u32 ssb_irqflag(struct ssb_device *dev)
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{
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u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
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if (tpsflag)
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return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
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else
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/* not irq supported */
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return 0x3f;
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}
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static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
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{
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struct ssb_bus *bus = rdev->bus;
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int i;
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for (i = 0; i < bus->nr_devices; i++) {
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struct ssb_device *dev;
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dev = &(bus->devices[i]);
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if (ssb_irqflag(dev) == irqflag)
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return dev;
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}
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return NULL;
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}
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/* Get the MIPS IRQ assignment for a specified device.
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* If unassigned, 0 is returned.
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* If disabled, 5 is returned.
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* If not supported, 6 is returned.
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*/
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unsigned int ssb_mips_irq(struct ssb_device *dev)
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{
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struct ssb_bus *bus = dev->bus;
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struct ssb_device *mdev = bus->mipscore.dev;
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u32 irqflag;
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u32 ipsflag;
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u32 tmp;
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unsigned int irq;
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irqflag = ssb_irqflag(dev);
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if (irqflag == 0x3f)
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return 6;
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ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
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for (irq = 1; irq <= 4; irq++) {
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tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
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if (tmp == irqflag)
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break;
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}
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if (irq == 5) {
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if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
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irq = 0;
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}
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return irq;
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}
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static void clear_irq(struct ssb_bus *bus, unsigned int irq)
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{
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struct ssb_device *dev = bus->mipscore.dev;
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/* Clear the IRQ in the MIPScore backplane registers */
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if (irq == 0) {
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ssb_write32(dev, SSB_INTVEC, 0);
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} else {
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ssb_write32(dev, SSB_IPSFLAG,
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ssb_read32(dev, SSB_IPSFLAG) |
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ipsflag_irq_mask[irq]);
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}
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}
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static void set_irq(struct ssb_device *dev, unsigned int irq)
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{
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unsigned int oldirq = ssb_mips_irq(dev);
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struct ssb_bus *bus = dev->bus;
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struct ssb_device *mdev = bus->mipscore.dev;
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u32 irqflag = ssb_irqflag(dev);
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BUG_ON(oldirq == 6);
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dev->irq = irq + 2;
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/* clear the old irq */
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if (oldirq == 0)
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ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
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else if (oldirq != 5)
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clear_irq(bus, oldirq);
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/* assign the new one */
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if (irq == 0) {
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ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
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} else {
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u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
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if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
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u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
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struct ssb_device *olddev = find_device(dev, oldipsflag);
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if (olddev)
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set_irq(olddev, 0);
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}
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irqflag <<= ipsflag_irq_shift[irq];
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irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
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ssb_write32(mdev, SSB_IPSFLAG, irqflag);
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}
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dev_dbg(dev->dev, "set_irq: core 0x%04x, irq %d => %d\n",
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dev->id.coreid, oldirq+2, irq+2);
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}
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static void print_irq(struct ssb_device *dev, unsigned int irq)
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{
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static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
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dev_dbg(dev->dev,
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"core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
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dev->id.coreid,
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irq_name[0], irq == 0 ? "*" : " ",
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irq_name[1], irq == 1 ? "*" : " ",
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irq_name[2], irq == 2 ? "*" : " ",
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irq_name[3], irq == 3 ? "*" : " ",
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irq_name[4], irq == 4 ? "*" : " ",
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irq_name[5], irq == 5 ? "*" : " ",
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irq_name[6], irq == 6 ? "*" : " ");
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}
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static void dump_irq(struct ssb_bus *bus)
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{
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int i;
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for (i = 0; i < bus->nr_devices; i++) {
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struct ssb_device *dev;
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dev = &(bus->devices[i]);
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print_irq(dev, ssb_mips_irq(dev));
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}
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}
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static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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if (ssb_extif_available(&bus->extif))
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mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
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else if (ssb_chipco_available(&bus->chipco))
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mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
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else
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mcore->nr_serial_ports = 0;
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}
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static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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struct ssb_sflash *sflash = &mcore->sflash;
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struct ssb_pflash *pflash = &mcore->pflash;
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/* When there is no chipcommon on the bus there is 4MB flash */
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if (!ssb_chipco_available(&bus->chipco)) {
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pflash->present = true;
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pflash->buswidth = 2;
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pflash->window = SSB_FLASH1;
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pflash->window_size = SSB_FLASH1_SZ;
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goto ssb_pflash;
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}
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/* There is ChipCommon, so use it to read info about flash */
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switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
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case SSB_CHIPCO_FLASHT_STSER:
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case SSB_CHIPCO_FLASHT_ATSER:
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dev_dbg(mcore->dev->dev, "Found serial flash\n");
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ssb_sflash_init(&bus->chipco);
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break;
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case SSB_CHIPCO_FLASHT_PARA:
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dev_dbg(mcore->dev->dev, "Found parallel flash\n");
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pflash->present = true;
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pflash->window = SSB_FLASH2;
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pflash->window_size = SSB_FLASH2_SZ;
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if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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& SSB_CHIPCO_CFG_DS16) == 0)
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pflash->buswidth = 1;
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else
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pflash->buswidth = 2;
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break;
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}
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ssb_pflash:
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if (sflash->present) {
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#ifdef CONFIG_BCM47XX
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bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);
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#endif
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} else if (pflash->present) {
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#ifdef CONFIG_BCM47XX
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bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);
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#endif
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ssb_pflash_data.width = pflash->buswidth;
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ssb_pflash_resource.start = pflash->window;
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ssb_pflash_resource.end = pflash->window + pflash->window_size;
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}
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}
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u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus = mcore->dev->bus;
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u32 pll_type, n, m, rate = 0;
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if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
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return ssb_pmu_get_cpu_clock(&bus->chipco);
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if (ssb_extif_available(&bus->extif)) {
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ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
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} else if (ssb_chipco_available(&bus->chipco)) {
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ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
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} else
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return 0;
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if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
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rate = 200000000;
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} else {
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rate = ssb_calc_clock_rate(pll_type, n, m);
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}
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if (pll_type == SSB_PLLTYPE_6) {
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rate *= 2;
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}
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return rate;
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}
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void ssb_mipscore_init(struct ssb_mipscore *mcore)
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{
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struct ssb_bus *bus;
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struct ssb_device *dev;
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unsigned long hz, ns;
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unsigned int irq, i;
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if (!mcore->dev)
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return; /* We don't have a MIPS core */
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dev_dbg(mcore->dev->dev, "Initializing MIPS core...\n");
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bus = mcore->dev->bus;
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hz = ssb_clockspeed(bus);
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if (!hz)
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hz = 100000000;
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ns = 1000000000 / hz;
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if (ssb_extif_available(&bus->extif))
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ssb_extif_timing_init(&bus->extif, ns);
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else if (ssb_chipco_available(&bus->chipco))
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ssb_chipco_timing_init(&bus->chipco, ns);
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/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
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for (irq = 2, i = 0; i < bus->nr_devices; i++) {
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int mips_irq;
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dev = &(bus->devices[i]);
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mips_irq = ssb_mips_irq(dev);
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if (mips_irq > 4)
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dev->irq = 0;
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else
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dev->irq = mips_irq + 2;
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if (dev->irq > 5)
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continue;
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switch (dev->id.coreid) {
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case SSB_DEV_USB11_HOST:
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/* shouldn't need a separate irq line for non-4710, most of them have a proper
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* external usb controller on the pci */
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if ((bus->chip_id == 0x4710) && (irq <= 4)) {
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set_irq(dev, irq++);
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}
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break;
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case SSB_DEV_PCI:
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case SSB_DEV_ETHERNET:
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case SSB_DEV_ETHERNET_GBIT:
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case SSB_DEV_80211:
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case SSB_DEV_USB20_HOST:
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/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
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if (irq <= 4) {
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set_irq(dev, irq++);
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break;
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}
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/* fallthrough */
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case SSB_DEV_EXTIF:
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set_irq(dev, 0);
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break;
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}
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}
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dev_dbg(mcore->dev->dev, "after irq reconfiguration\n");
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dump_irq(bus);
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ssb_mips_serial_init(mcore);
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ssb_mips_flash_detect(mcore);
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||
|
|
}
|