700 lines
16 KiB
C
700 lines
16 KiB
C
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/*
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* DSPG DBMD4/DBMD6/DBMD8 UART interface driver
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*
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* Copyright (C) 2014 DSP Group
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* #define DEBUG */
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#if IS_ENABLED(CONFIG_OF)
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#include <linux/of.h>
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#endif
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#include <linux/tty.h>
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#include <linux/kthread.h>
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <linux/firmware.h>
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#include "dbmdx-interface.h"
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#include "dbmdx-va-regmap.h"
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#include "dbmdx-uart.h"
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/* baud rate used during fw upload */
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#define UART_TTY_MAX_BAUD_RATE 4000000
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/* number of stop bits during boot-up */
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#define UART_TTY_BOOT_STOP_BITS 1
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/* number of stop bits during normal operation */
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#define UART_TTY_NORMAL_STOP_BITS 1
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/* parity during boot-up */
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#define UART_TTY_BOOT_PARITY 0
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/* parity during normal operation */
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#define UART_TTY_NORMAL_PARITY 0
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static const u8 read_divider[6] = {0x5a, 0x07, 0x0c, 0x00, 0x00, 0x00};
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static int dbmd4_uart_prepare_boot(struct dbmdx_private *p)
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{
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struct dbmdx_uart_private *uart_p =
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(struct dbmdx_uart_private *)p->chip->pdata;
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dev_dbg(uart_p->dev, "%s\n", __func__);
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uart_p->boot_baud_rate = UART_TTY_MAX_BAUD_RATE;
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uart_p->boot_parity = UART_TTY_BOOT_PARITY;
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uart_p->boot_stop_bits = UART_TTY_BOOT_STOP_BITS;
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uart_p->normal_parity = UART_TTY_NORMAL_PARITY;
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uart_p->normal_stop_bits = UART_TTY_NORMAL_STOP_BITS;
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dev_dbg(uart_p->dev, "%s: lookup TTY band rate = %d\n",
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__func__, uart_p->boot_baud_rate);
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return 0;
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}
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#define DBMD4_UART_SYNC_LENGTH 20
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static int dbmd4_uart_sync(struct dbmdx_private *p)
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{
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struct dbmdx_uart_private *uart_p =
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(struct dbmdx_uart_private *)p->chip->pdata;
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int rc;
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u8 sync_buf[DBMD4_UART_SYNC_LENGTH];
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u8 rx_divider[6];
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u32 divider;
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u32 expected_divider;
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u32 clock_rate;
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dev_info(p->dev, "%s: start boot sync\n", __func__);
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memset(sync_buf, 0, sizeof(sync_buf));
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memset(rx_divider, 0, sizeof(rx_divider));
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rc = uart_write_data(p, (void *)sync_buf, DBMD4_UART_SYNC_LENGTH);
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if (rc != DBMD4_UART_SYNC_LENGTH)
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dev_err(uart_p->dev, "%s: sync buffer not sent correctly\n",
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__func__);
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/* check if synchronization succeeded */
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usleep_range(300, 400);
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rc = uart_wait_for_ok(p);
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if (rc != 0) {
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dev_err(p->dev, "%s: boot fail: no sync found err = %d\n",
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__func__, rc);
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return -EAGAIN;
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}
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uart_flush_rx_fifo(uart_p);
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clock_rate = p->master_pll_rate;
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if (clock_rate == 0) {
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dev_info(uart_p->dev,
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"%s: No master clock defined, cannot verify divider\n",
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__func__);
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return 0;
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}
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/* Read divider register to verify that baud rate was locked
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* successfully
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*/
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rc = uart_write_data(p, read_divider, sizeof(read_divider));
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if (rc != sizeof(read_divider)) {
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dev_err(uart_p->dev, "%s: could not read divider (send)\n",
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__func__);
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return -EAGAIN;
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}
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rc = uart_read_data(p, rx_divider, 6);
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if (rc < 0) {
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dev_err(uart_p->dev,
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"%s: could not read divider data (receive)\n",
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__func__);
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return -EAGAIN;
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}
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if ((rx_divider[0] != read_divider[0]) ||
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(rx_divider[1] != read_divider[1])) {
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dev_err(uart_p->dev,
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"%s: could not read divider data (mismatch)\n",
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__func__);
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dev_err(uart_p->dev,
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"%s: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
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__func__, rx_divider[0], rx_divider[1], rx_divider[2],
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rx_divider[3], rx_divider[4], rx_divider[5]);
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return -EAGAIN;
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}
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divider = (u32)(rx_divider[2]) +
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(((u32)(rx_divider[3]) << 8) & 0x0000ff00) +
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(((u32)(rx_divider[4]) << 16) & 0x00ff0000) +
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(((u32)(rx_divider[5]) << 24) & 0xff000000);
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expected_divider = ((u32)(clock_rate / uart_p->normal_baud_rate) % 16);
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if (expected_divider != divider) {
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dev_err(uart_p->dev,
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"%s: divider mismatch: expected %u, received %u\n",
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__func__, expected_divider, divider);
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}
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dev_dbg(p->dev, "%s: boot sync successfully\n", __func__);
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return 0;
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}
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static int dbmd4_uart_reset(struct dbmdx_private *p)
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{
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struct dbmdx_uart_private *uart_p =
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(struct dbmdx_uart_private *)p->chip->pdata;
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int ret = 0;
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dev_dbg(uart_p->dev, "%s\n", __func__);
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/* set baudrate to FW upload speed */
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ret = uart_set_speed_host_only(p, DBMDX_VA_SPEED_MAX);
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if (ret) {
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dev_err(p->dev, "%s: failed configure uart\n",
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__func__);
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return -EIO;
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}
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uart_flush_rx_fifo(uart_p);
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dev_dbg(p->dev, "%s: start boot sync\n", __func__);
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if (!(p->boot_mode & DBMDX_BOOT_MODE_RESET_DISABLED))
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/* reset the chip */
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p->reset_sequence(p);
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/* delay before sending commands */
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if (p->clk_get_rate(p, DBMDX_CLK_MASTER) <= 32768)
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msleep(DBMDX_MSLEEP_UART_D4_AFTER_RESET_32K);
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else
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usleep_range(DBMDX_USLEEP_UART_D4_AFTER_RESET,
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DBMDX_USLEEP_UART_D4_AFTER_RESET + 5000);
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if (!(p->cur_boot_options & DBMDX_BOOT_OPT_VA_NO_UART_SYNC)) {
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/* check if firmware sync is ok */
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ret = dbmd4_uart_sync(p);
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if (ret != 0) {
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dev_err(uart_p->dev, "%s: sync failed\n",
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__func__);
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return -EAGAIN;
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}
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dev_dbg(p->dev, "%s: boot sync successful\n", __func__);
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}
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uart_flush_rx_fifo(uart_p);
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return 0;
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}
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static int dbmd4_uart_load_firmware(const void *fw_data, size_t fw_size,
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struct dbmdx_private *p, const void *checksum,
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size_t chksum_len)
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{
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struct dbmdx_uart_private *uart_p =
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(struct dbmdx_uart_private *)p->chip->pdata;
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int ret;
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/* verify chip id */
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if (p->cur_boot_options & DBMDX_BOOT_OPT_VERIFY_CHIP_ID) {
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ret = uart_verify_chip_id(p);
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if (ret < 0) {
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dev_err(p->dev, "%s: couldn't verify chip id\n",
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__func__);
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return -EIO;
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}
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}
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if (!(p->cur_boot_options & DBMDX_BOOT_OPT_DONT_CLR_CRC)) {
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/* send CRC clear command */
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ret = send_uart_cmd_boot(p, DBMDX_CLEAR_CHECKSUM);
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if (ret) {
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dev_err(p->dev, "%s: failed to clear CRC\n", __func__);
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return -EIO;
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}
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}
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/* send firmware */
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ret = uart_write_data(p, fw_data, fw_size - 4);
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if (ret != (fw_size - 4)) {
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dev_err(p->dev, "%s: -----------> load firmware error\n",
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__func__);
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return -EIO;
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}
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/* verify checksum */
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if (checksum && !(p->cur_boot_options &
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DBMDX_BOOT_OPT_DONT_VERIFY_CRC)) {
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ret = uart_verify_boot_checksum(p, checksum, chksum_len);
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if (ret < 0) {
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dev_err(uart_p->dev,
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"%s: could not verify checksum\n",
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__func__);
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return -EIO;
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}
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}
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dev_info(p->dev, "%s: ---------> firmware loaded\n", __func__);
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return 0;
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}
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static int dbmd4_uart_boot(const void *fw_data, size_t fw_size,
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struct dbmdx_private *p, const void *checksum,
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size_t chksum_len, int load_fw)
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{
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struct dbmdx_uart_private *uart_p =
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(struct dbmdx_uart_private *)p->chip->pdata;
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int reset_retry = RETRY_COUNT;
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int fw_load_retry = RETRY_COUNT;
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int ret;
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dev_dbg(uart_p->dev, "%s\n", __func__);
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do {
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if ((p->boot_mode & DBMDX_BOOT_MODE_RESET_DISABLED) &&
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(fw_load_retry != RETRY_COUNT)) {
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fw_load_retry = -1;
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break;
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}
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reset_retry = RETRY_COUNT;
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do {
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ret = dbmd4_uart_reset(p);
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if (ret == 0)
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break;
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} while (--reset_retry);
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/* Unable to reset device */
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if (reset_retry <= 0) {
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dev_err(p->dev, "%s, reset device err\n",
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__func__);
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return -ENODEV;
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}
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/* stop here if firmware does not need to be reloaded */
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if (load_fw) {
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ret = dbmd4_uart_load_firmware(fw_data, fw_size, p,
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checksum, chksum_len);
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if (ret != 0) {
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dev_err(p->dev, "%s: failed to load firwmare\n",
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__func__);
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continue;
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}
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}
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if (!(p->cur_boot_options &
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DBMDX_BOOT_OPT_DONT_SEND_START_BOOT)) {
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/* send boot command */
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ret = send_uart_cmd_boot(p, DBMDX_FIRMWARE_BOOT);
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if (ret) {
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dev_err(p->dev,
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"%s: booting the firmware failed\n", __func__);
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continue;
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}
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}
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usleep_range(DBMDX_USLEEP_UART_D4_AFTER_LOAD_FW,
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DBMDX_USLEEP_UART_D4_AFTER_LOAD_FW + 1000);
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/* everything went well */
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break;
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} while (--fw_load_retry);
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if (fw_load_retry <= 0) {
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dev_err(p->dev, "%s: exceeded max attepmts to load fw\n",
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__func__);
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return -EIO;
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}
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return 0;
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}
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static int dbmd4_uart_reset_post_pll_divider(struct dbmdx_private *p)
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{
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struct dbmdx_uart_private *uart_p =
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(struct dbmdx_uart_private *)p->chip->pdata;
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int ret;
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dev_dbg(uart_p->dev, "%s\n", __func__);
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ret = send_uart_cmd_va(p,
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DBMDX_VA_GENERAL_CONFIGURATION_2,
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&uart_p->post_pll_div);
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if (ret < 0) {
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dev_err(p->dev,
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"%s: failed to get post pll divider\n",
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__func__);
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return ret;
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}
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ret = send_uart_cmd_va(p,
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DBMDX_VA_GENERAL_CONFIGURATION_2 |
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(uart_p->post_pll_div & ~DBMDX_POST_PLL_DIV_MASK),
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NULL);
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|
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed to get post pll divider\n",
|
||
|
|
__func__);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmd4_uart_restore_post_pll_divider(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
ret = send_uart_cmd_va(p,
|
||
|
|
DBMDX_VA_GENERAL_CONFIGURATION_2 |
|
||
|
|
uart_p->post_pll_div,
|
||
|
|
NULL);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed to restore post pll divider\n",
|
||
|
|
__func__);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmd4_uart_switch_to_buffering_speed(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
ret = dbmd4_uart_reset_post_pll_divider(p);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed, cannot reset post pll divider\n",
|
||
|
|
__func__);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = uart_set_speed(p, DBMDX_VA_SPEED_BUFFERING);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(uart_p->dev, "%s:failed setting speed %x\n",
|
||
|
|
__func__, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmd4_uart_switch_to_normal_speed(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
ret = uart_set_speed(p, DBMDX_VA_SPEED_NORMAL);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(uart_p->dev, "%s:failed setting speed %x\n",
|
||
|
|
__func__, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
ret = dbmd4_uart_restore_post_pll_divider(p);
|
||
|
|
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed, cannot restore post pll divider\n",
|
||
|
|
__func__);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmd4_uart_prepare_buffering(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
if (p->pdata->uart_low_speed_enabled) {
|
||
|
|
|
||
|
|
ret = dbmd4_uart_switch_to_buffering_speed(p);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed to send change speed command\n",
|
||
|
|
__func__);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
out:
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmd4_uart_finish_buffering(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
if (p->pdata->uart_low_speed_enabled) {
|
||
|
|
|
||
|
|
ret = dbmd4_uart_switch_to_normal_speed(p);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed to send change speed command\n",
|
||
|
|
__func__);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
out:
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static int dbmd4_uart_prepare_amodel_loading(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
if (p->pdata->uart_low_speed_enabled) {
|
||
|
|
|
||
|
|
ret = dbmd4_uart_switch_to_buffering_speed(p);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed to send change speed command\n",
|
||
|
|
__func__);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
out:
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmd4_uart_finish_amodel_loading(struct dbmdx_private *p)
|
||
|
|
{
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)p->chip->pdata;
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
dev_dbg(uart_p->dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
if (p->pdata->uart_low_speed_enabled) {
|
||
|
|
|
||
|
|
ret = dbmd4_uart_switch_to_normal_speed(p);
|
||
|
|
|
||
|
|
if (ret) {
|
||
|
|
dev_err(p->dev,
|
||
|
|
"%s: failed to send change speed command\n",
|
||
|
|
__func__);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
out:
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_PM_SLEEP)
|
||
|
|
static int dbmdx_uart_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct chip_interface *ci = dev_get_drvdata(dev);
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)ci->pdata;
|
||
|
|
|
||
|
|
dev_dbg(dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
uart_interface_suspend(uart_p);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmdx_uart_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct chip_interface *ci = dev_get_drvdata(dev);
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)ci->pdata;
|
||
|
|
|
||
|
|
dev_dbg(dev, "%s\n", __func__);
|
||
|
|
uart_interface_resume(uart_p);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
#define dbmdx_uart_suspend NULL
|
||
|
|
#define dbmdx_uart_resume NULL
|
||
|
|
#endif /* CONFIG_PM_SLEEP */
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_PM)
|
||
|
|
static int dbmdx_uart_runtime_suspend(struct device *dev)
|
||
|
|
{
|
||
|
|
struct chip_interface *ci = dev_get_drvdata(dev);
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)ci->pdata;
|
||
|
|
|
||
|
|
dev_dbg(dev, "%s\n", __func__);
|
||
|
|
|
||
|
|
uart_interface_suspend(uart_p);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dbmdx_uart_runtime_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct chip_interface *ci = dev_get_drvdata(dev);
|
||
|
|
struct dbmdx_uart_private *uart_p =
|
||
|
|
(struct dbmdx_uart_private *)ci->pdata;
|
||
|
|
|
||
|
|
dev_dbg(dev, "%s\n", __func__);
|
||
|
|
uart_interface_resume(uart_p);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
#define dbmdx_uart_runtime_suspend NULL
|
||
|
|
#define dbmdx_uart_runtime_resume NULL
|
||
|
|
#endif /* CONFIG_PM */
|
||
|
|
|
||
|
|
|
||
|
|
static const struct dev_pm_ops dbmdx_uart_pm = {
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(dbmdx_uart_suspend, dbmdx_uart_resume)
|
||
|
|
SET_RUNTIME_PM_OPS(dbmdx_uart_runtime_suspend,
|
||
|
|
dbmdx_uart_runtime_resume, NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static int dbmd4_uart_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
struct dbmdx_uart_private *p;
|
||
|
|
struct chip_interface *ci;
|
||
|
|
|
||
|
|
rc = uart_common_probe(pdev, "dbmd4 uart probe thread");
|
||
|
|
|
||
|
|
if (rc < 0)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
ci = dev_get_drvdata(&pdev->dev);
|
||
|
|
p = (struct dbmdx_uart_private *)ci->pdata;
|
||
|
|
|
||
|
|
/* fill in chip interface functions */
|
||
|
|
p->chip.prepare_boot = dbmd4_uart_prepare_boot;
|
||
|
|
p->chip.prepare_amodel_loading = dbmd4_uart_prepare_amodel_loading;
|
||
|
|
p->chip.finish_amodel_loading = dbmd4_uart_finish_amodel_loading;
|
||
|
|
p->chip.prepare_buffering = dbmd4_uart_prepare_buffering;
|
||
|
|
p->chip.finish_buffering = dbmd4_uart_finish_buffering;
|
||
|
|
p->chip.boot = dbmd4_uart_boot;
|
||
|
|
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static const struct of_device_id dbmd_4_8_uart_of_match[] = {
|
||
|
|
{ .compatible = "dspg,dbmdx-uart", },
|
||
|
|
{ .compatible = "dspg,dbmd4-uart", },
|
||
|
|
{ .compatible = "dspg,dbmd6-uart", },
|
||
|
|
{ .compatible = "dspg,dbmd8-uart", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
#if IS_ENABLED(CONFIG_SND_SOC_DBMDX)
|
||
|
|
MODULE_DEVICE_TABLE(of, dbmd_4_8_uart_of_match);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static struct platform_driver dbmd_4_8_uart_platform_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "dbmd_4_8-uart",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
#if IS_ENABLED(CONFIG_OF)
|
||
|
|
.of_match_table = dbmd_4_8_uart_of_match,
|
||
|
|
#endif
|
||
|
|
.pm = &dbmdx_uart_pm,
|
||
|
|
},
|
||
|
|
.probe = dbmd4_uart_probe,
|
||
|
|
.remove = uart_common_remove,
|
||
|
|
};
|
||
|
|
|
||
|
|
#if (IS_ENABLED(CONFIG_SND_SOC_DBMDX) && !IS_MODULE(CONFIG_SND_SOC_DBMDX))
|
||
|
|
static int __init dbmd_4_8_modinit(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&dbmd_4_8_uart_platform_driver);
|
||
|
|
}
|
||
|
|
module_init(dbmd_4_8_modinit);
|
||
|
|
|
||
|
|
static void __exit dbmd_4_8_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&dbmd_4_8_uart_platform_driver);
|
||
|
|
}
|
||
|
|
module_exit(dbmd_4_8_exit);
|
||
|
|
#else
|
||
|
|
int dbmd4_uart_init_interface(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&dbmd_4_8_uart_platform_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
void dbmd4_uart_deinit_interface(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&dbmd_4_8_uart_platform_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
int (*dbmdx_init_interface)(void) = &dbmd4_uart_init_interface;
|
||
|
|
void (*dbmdx_deinit_interface)(void) = &dbmd4_uart_deinit_interface;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("DSPG DBMD4/DBMD6/DBMD8 UART interface driver");
|
||
|
|
MODULE_LICENSE("GPL");
|